Wafer-Level 3D ASIC Substrate for Fine-Line High-Density Packaging
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Solution Overview
Problem
Traditional PCB substrate packaging technologies face limitations in line width and spacing, high cost, long production times, and risk of chip damage, failing to meet the demands of high-functional integration and customization.
Innovation Solution
A wafer-level ASIC 3D integrated substrate is developed with reduced line width and spacing to 1.5 μm, featuring a multi-layer structure with conductive pillars and bridge ICs, enabling high-density packaging and integration, and a method that includes forming dielectric and metal wire layers, molding, and peeling off carriers to expose metal wire layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional PCB substrate packaging technology is used, then the manufacturing process is simple and cost is low, but the line width and spacing are limited to more than 50 μm, preventing high integration
Solution Approach 1:
The patent transitions from traditional 2D PCB substrate to a 3D integrated substrate structure with multiple wiring layers (first wiring layer, second wiring layer) stacked vertically and connected through conductive pillars. This dimensional change enables high integration density while maintaining manufacturability through standardized layer-by-layer fabrication processes.
2Manufacturing precision
If fan-out wafer-level packaging technology is used to achieve high integration, then the line width and spacing can be reduced to 20 μm, but the cost increases and production time is extended
Solution Approach 1:
The patent performs preliminary customization of the substrate structure before chip packaging. The multi-layer wiring structure, conductive pillars, and bonding pads are pre-formed on the substrate, enabling subsequent chip mounting to proceed rapidly without requiring complex post-packaging modifications or rework, thus reducing overall production time.
Solution Approach 2:
The substrate is divided into functionally independent layers: first wiring layer for signal routing, second wiring layer for power/ground, conductive pillars for vertical interconnection, and bonding pads for chip attachment. This segmentation allows parallel processing of different layers and simplifies the overall manufacturing workflow.
3Manufacturing precision
If advanced 2.5D & fan out wafer-level packaging technology is used, then high integration is achieved, but the cost becomes high
Solution Approach 1:
The patent optimizes key parameters including reducing line width and spacing to achieve high integration density, controlling wiring layer thickness at 15-40 μm, and setting molding layer thickness at 50-100 μm. These parameter changes enable high precision manufacturing while maintaining cost-effectiveness through efficient material usage and standardized process parameters.
4Area of stationary object
If traditional PCB substrate is used, then the manufacturing process is simple, but the substrate size becomes large to accommodate I/O interfaces
Solution Approach 1:
The patent resolves the area-complexity tradeoff by stacking multiple wiring layers vertically and connecting them through conductive pillars. This 3D architecture consolidates numerous I/O interfaces and signal routes into a compact vertical structure, dramatically reducing the substrate footprint while managing complexity through modular layer design.
Data Source
AI summary
A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.