Wafer-Level Antenna Package Structure for Thinner Die Integration
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in efficiently integrating antenna structures with semiconductor dies at the wafer level, leading to increased thickness and production costs due to the complexity of antenna substrate formation and die attachment processes.
Innovation Solution
A method for wafer-level packaging that involves a carrier with a buffer layer, an antenna substrate structure with multiple antenna elements, and a redistribution layer, where the semiconductor die is attached to the redistribution layer and electrically connected to the antenna substrate through conductive pillars and vias, allowing for efficient integration and reduced thickness of the package structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If antenna structures are integrated with semiconductor dies at the wafer level, then manufacturing efficiency is improved, but the complexity of antenna substrate formation and die attachment processes increases
Solution Approach 1:
The patent combines the antenna substrate formation and die attachment processes into a single integrated wafer-level packaging operation. Multiple antenna elements are formed directly on the wafer carrier along with the semiconductor dies, eliminating the need for separate substrate preparation and attachment steps that would otherwise be required for individual devices.
Solution Approach 2:
The wafer carrier serves multiple functions simultaneously: it acts as the substrate for forming both the antenna elements and the semiconductor dies, provides mechanical support during processing, and enables parallel fabrication of multiple devices. This multi-functional approach reduces the number of separate process steps required.
2Device complexity
If traditional packaging methods are used, then process simplicity is maintained, but package thickness increases
Solution Approach 1:
The patent transitions from traditional three-dimensional stacked packaging to a planar two-dimensional integration approach at the wafer level. Antenna elements and semiconductor dies are formed side-by-side on the same wafer plane, reducing the vertical thickness of the final package while maintaining all necessary functional connections.
3Ease of manufacture
If conventional die attachment processes are used, then manufacturing simplicity is maintained, but production costs increase
Solution Approach 1:
The patent performs preliminary formation of antenna elements, conductive vias, and semiconductor dies all at the wafer level before final packaging. This advance preparation eliminates the need for costly post-dicing individual device assembly and reduces material waste by enabling bulk processing of multiple devices simultaneously.
Data Source
AI summary
A package structure includes a semiconductor die, an antenna substrate structure, a redistribution layer. The semiconductor die laterally encapsulated by a first encapsulant. The antenna substrate structure disposed over the semiconductor die, wherein the antenna substrate structure includes a first type of antenna, and a second type of antenna disposed on a side of the antenna substrate structure facing away from the semiconductor die. The redistribution layer disposed between the semiconductor die and the antenna substrate structure. The semiconductor die, the first type of antenna, and the second type of antenna are electrically coupled through the redistribution layer. The polarization of radiation emitted by the first type of antenna is perpendicular to a polarization of radiation emitted by the second type of antenna.