Wafer-Level Back-End Fabrication for Infrared Focal Plane Arrays
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Solution Overview
Problem
Traditional back-end fabrication of focal plane arrays is time-consuming and costly due to serial processing at the die-level, which leads to inefficiencies and damage during backside processing without a carrier.
Innovation Solution
Performing the majority of back-end manufacturing steps, including polishing, substrate removal, and coating, at the wafer-level before singulation, using carrier wafers for mechanical support and protection, and then hybridizing individual dies with a read-out integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If back-end fabrication is performed serially at the die-level, then each die can be processed individually with precise control, but the overall production time and cost increase significantly
Solution Approach 1:
The patent merges multiple individual die processing steps into a single wafer-level processing operation. By keeping dies connected on the wafer substrate during back-end fabrication, all dies undergo thinning, polishing, coating, and hybridization simultaneously rather than individually, thereby maintaining processing quality while dramatically improving throughput and reducing costs
Solution Approach 2:
The wafer-level processing approach allows a single processing tool to perform back-end fabrication on multiple dies simultaneously. The processing system achieves multi-functionality by handling entire wafer arrays through coating, thinning, and hybridization in one operation, eliminating the need for repeated individual die handling and making the process universally applicable to all dies on the wafer
2Productivity
If wafer-level back-end processing is performed without a carrier, then processing speed increases, but damage occurs to the backside optical surface
Solution Approach 1:
The patent applies a protective coating to the backside optical surface before back-end processing begins. This preliminary protective action prevents damage during subsequent thinning and polishing operations, allowing rapid wafer-level processing while maintaining surface integrity. The coating is applied in advance to all dies simultaneously on the wafer
Solution Approach 2:
The protective coating acts as an intermediary layer between the processing tools and the backside optical surface. This intermediate protective layer absorbs mechanical stresses and prevents direct contact damage during thinning and polishing, enabling fast wafer-level processing without compromising the underlying optical surface
3Manufacturing precision
If traditional serial die-level processing is used, then each step can be carefully controlled, but the cumulative time and cost for processing multiple dies increases
Solution Approach 1:
The patent combines multiple sequential die-level operations into a single parallel wafer-level operation. Coating, thinning, polishing, and hybridization are merged into unified wafer-level processes where all dies are processed simultaneously, reducing the cumulative time from multiple sequential steps to a single parallel operation while maintaining quality through wafer-level process control
Data Source
AI summary
Systems and methods may be provided for fabricating infrared focal plane arrays. The methods include providing a device wafer, applying a coating to the device wafer, mounting the device wafer to a first carrier wafer, thinning the device wafer while the device wafer is mounted to the first carrier wafer, releasing the device wafer from the first carrier wafer, singulating the device wafer into individual dies, each die having an infrared focal plane array, and hybridizing the individual dies to a read out integrated circuit.