Wafer-Level Back-to-Front Electrical Connections for Power MOSFETs

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Solution Overview

Problem

Conventional semiconductor packaging methods for vertical power MOSFET devices are expensive, time-consuming, and inefficient due to the need for preformed U-shaped clips and solder bumps, which limit heat dissipation and increase production costs, especially in high current applications.

Innovation Solution

A wafer-level chip scale packaging process that enables back-to-front electrical connections using conductive materials like carbon or carbon nanotubes, eliminating the need for preformed clips and solder bumps, and allowing for batch handling with reduced equipment and lower costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional epoxy or solder die attach with aluminum or gold wire bonding is used, then packaging reliability is maintained, but manufacturing cost and complexity increase

Engineering Contradiction:
Improvemanufacturing costVSAvoidpackaging process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges multiple discrete packaging steps (die attach, wire bonding, encapsulation) into a single wafer-level process where conductive material is applied directly to the wafer surface before singulation, eliminating the need for separate assembly operations on individual devices

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductive material is applied to the wafer surface in advance before the wafer is cut into individual devices, so that electrical connections are already in place when devices are separated, eliminating the need for post-singulation assembly operations

Inventive Principle:
Principle #10Preliminary action

2Temperature

If preformed U-shaped clips and solder bumps are used for electrical connections, then electrical connectivity is ensured, but heat dissipation capability deteriorates

Engineering Contradiction:
Improveheat dissipationVSAvoidelectrical connection reliability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent removes the intermediate U-shaped clip structure entirely, allowing the drain electrode to contact the mounting substrate directly through applied conductive material, creating a shorter and more efficient thermal path while maintaining electrical connectivity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from point-contact electrical connections (solder bumps) to a planar surface contact approach where conductive material is applied across the entire drain surface, increasing the contact area for both electrical and thermal transfer

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If different U-shaped clips are used for different die sizes, then electrical connection adaptability is improved, but manufacturing complexity and space requirements increase

Engineering Contradiction:
Improvedie size adaptabilityVSAvoidtooling complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal packaging process where the same conductive material application technique works for all die sizes, eliminating the need for different clip designs and reducing tooling complexity while maintaining adaptability to various device dimensions

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This process reduces production costs and complexity, enhances heat dissipation, and is flexible across different die sizes without requiring tooling changes, while minimizing thermal stress and mechanical damage to semiconductor chips.

Implementation Method 1

conductive material 110, which will be added later in the process... provide electrical connection from the drain electrode 107

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

mounting the semiconductor wafer 100 to a package substrate 101

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS8426960B2Wafer level chip scale packaging
Publication Date: 2013.04.23 ALPHA & OMEGA SEMICONDUCTOR LTD
  • US8426960B2 patent drawing
  • US8426960B2 patent drawing
  • US8426960B2 patent drawing

AI summary

A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.