Wafer-Level Build-Up Routing for Solderless Die-to-Terminal Packaging
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Solution Overview
Problem
Conventional semiconductor device packaging processes face challenges with high resistance paths and defects due to misalignment and process variables, particularly in flip chip and wire bonded packages, which increase the likelihood of scrapped devices as devices shrink in size.
Innovation Solution
A semiconductor device package is formed with a build-up routing layer on the wafer level, where connection and trace level conductors directly contact bond pads, eliminating the need for solder joints or bond wires, and mold compound covers the conductors, exposing terminals from the package body for direct electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder joints and bond wires are used to connect semiconductor dies to package terminals, then electrical connections can be established, but high resistance paths and defects occur due to misalignment and process variables
Solution Approach 1:
The patent extracts and eliminates solder joints and bond wires from the packaging process. Instead of using these intermediate connection elements, the invention forms direct conductive paths through the package substrate that connect semiconductor die pads directly to package terminals, removing the sources of misalignment and process variability associated with soldering and wire bonding operations
Solution Approach 2:
The patent creates an asymmetric packaging architecture where the connection path differs fundamentally from conventional approaches. Rather than symmetric use of solder joints for both electrical and mechanical connection, the invention uses asymmetric direct traces for electrical connection combined with separate underfill material for mechanical support, optimizing each function independently
2Productivity
If devices are shrunk in size to improve integration, then more devices can be packed, but the likelihood of defects and scrapped devices increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming conductive traces and pads in the package substrate before mounting the semiconductor dies. This allows precise alignment to be established in advance, and the underfill material to be applied beforehand to provide mechanical support, thereby preventing defects that would otherwise occur with smaller, more vulnerable devices
Solution Approach 2:
The patent applies underfill material beforehand to cushion and support smaller semiconductor devices during and after mounting. This protective layer compensates for the reduced mechanical robustness of smaller devices, preventing damage and connection failures that would increase defect rates in high-density packaging
3Ease of manufacture
If conventional packaging processes with multiple steps are used, then semiconductor devices can be packaged, but manufacturing complexity and time increase
Solution Approach 1:
The patent merges multiple conventional packaging steps into a unified process. The conductive traces, pads, and mechanical support structures are all formed in the package substrate before die mounting, combining what would otherwise be separate operations into a single integrated substrate preparation and assembly process
Solution Approach 2:
The patent performs preliminary substrate preparation including trace formation, pad creation, and underfill application before semiconductor die mounting. This resequencing allows these operations to be performed on the substrate alone rather than requiring additional steps after die attachment, thereby reducing total manufacturing cycle time
Data Source
AI summary
An example semiconductor device package includes a semiconductor die having bond pads on a device side surface, and a build-up routing layer on the semiconductor die including: connection level conductors directly contacting the bond pads; trace level conductors on the connection level conductors directly contacting distal ends of the connection level conductors; dielectric material surrounding the connection level conductors and the trace level conductors; terminals formed of portions of a top layer of the trace level conductors having a board side surface exposed from the dielectric material, wherein an electrical connection between the terminals and the bond pads is formed without a solder joint or a bond wire; and mold compound covering a portion of the semiconductor die, the trace level conductors and the connection level conductors of the build-up routing layer, wherein the board side surface of the terminals is exposed from the mold compound.