Wafer-Level Chip Package Bump Assemblies for Standoff Height Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wafer-level packaging techniques are limited in their application to larger integrated circuit chips due to issues such as die collapse and solder bridging, which restrict higher input/output pin counts and reliability.
Innovation Solution
The fabrication of wafer-level chip-scale package semiconductor devices with bump assemblies that include both core-less solder bumps and solder bumps with cores, strategically positioned to maintain standoff height and reduce stress, thereby preventing die collapse and allowing for increased I/O pin counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer-level packaging is applied to larger integrated circuit chips, then chip-scale packaging benefits are achieved, but die collapse occurs during reflow
Solution Approach 1:
The patent applies different bump configurations to different locations on the chip. Coreless solder bumps are used in certain areas while solder bumps with cores are used in other areas, particularly at corners and edges. This local differentiation allows the package to achieve high I/O pin counts while preventing die collapse through strategic placement of supportive cores where stress is most critical.
Solution Approach 2:
The patent employs a composite bump structure combining two types of solder bumps: coreless solder bumps for electrical connection and solder bumps with internal cores for mechanical support. This composite approach allows the package to simultaneously achieve high electrical connectivity and structural stability, resolving the contradiction between reliability and die stability.
2Quantity of substance
If higher I/O pin counts are achieved on larger chips, then packaging capabilities are improved, but solder bridging occurs between adjacent bumps
Solution Approach 1:
The patent uses different bump assemblies in different locations to optimize both pin count and reliability. By strategically placing coreless bumps and bumps with cores in specific patterns, the design achieves high I/O density while maintaining adequate spacing and structural support to prevent solder bridging during the reflow process.
3Reliability
If standoff height is maintained, then package reliability is improved, but additional structural elements increase device complexity
Solution Approach 1:
The patent maintains standoff height by incorporating cores within selected solder bumps rather than adding separate structural elements. This approach preserves the mechanical support function while minimizing additional complexity, as the cores are integrated within the existing bump structure rather than adding discrete components.
Data Source
AI summary
Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.