Wafer-Level Chip Package Integration for Operational Consistency
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Solution Overview
Problem
Semiconductor devices combining multiple chip packages often fail due to difficulties in determining the operational capability of individual chip packages, leading to defective integrated circuits when capable and defective devices are joined.
Innovation Solution
The solution involves forming chip packages from the same base and capping wafers using eutectic bonding, followed by separation and alignment, ensuring all chip packages within the semiconductor device are derived from the same materials and processes, and bonding them together with a molding compound to enhance operational consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chip packages are combined into an integrated circuit from different processes and conditions, then the integrated circuit can provide diverse functionality, but the reliability decreases because operational performance cannot be consistently determined
Solution Approach 1:
The integrated circuit is segmented into multiple chip packages, each performing different functions. These segments are formed separately through wafer-level processing and then combined, allowing functional diversity while maintaining consistent formation conditions for each segment
Solution Approach 2:
Chip packages are preliminarily formed and tested at the wafer level before final integration. This preliminary action ensures that only properly functioning chip packages are selected and combined into the final integrated circuit, maintaining reliability while achieving functional diversity
2Ease of manufacture
If chip packages are formed under different conditions, then manufacturing flexibility increases, but manufacturing precision decreases leading to defective integrated circuits
Solution Approach 1:
Multiple chip packages are merged into a single integrated circuit structure through wafer-level integration. This combining approach ensures all chip packages undergo the same formation processes under identical conditions, achieving consistent manufacturing precision while maintaining the flexibility to include different chip package types
3Device complexity
If operational capability of individual chip packages is difficult to determine, then device complexity decreases, but reliability decreases due to defective devices being joined
Solution Approach 1:
The chip packages perform self-testing through built-in test structures and procedures during the wafer-level formation process. This self-service approach allows operational capability to be determined automatically without complex external testing equipment, reducing testing complexity while ensuring reliable defect detection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the likelihood that all chip packages in the semiconductor device are capable of performing intended operations, reducing the likelihood of defective final devices and improving the reliability of integrated circuits.
Implementation Method 1
a capping wafer eutectic bonded to the base wafer
Data Source
AI summary
A method of forming a semiconductor device comprises forming a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion. The method also comprises forming a capping wafer comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion. The method further comprises eutectic bonding the capping wafer and the base wafer to form a wafer package. The method additionally comprises dicing the wafer package into a first chip package, a second chip package, and a third chip package. The method also comprises placing the first chip package, the second chip package, and the third chip package onto a substrate.