Wafer-Level Chip Package Manufacturing with Precise Gap Spacing
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Solution Overview
Problem
Conventional chip packaging methods are time-consuming and prone to alignment offset issues due to the complex and labor-intensive process of arranging semiconductor dies on a carrier board and subsequent dicing.
Innovation Solution
A method involving a wafer with conductive bumps, where the wafer is thinned and diced to form chips, which are then disposed on a substrate with conductive bumps facing the substrate, and an insulating layer is formed to fill gaps between chips, eliminating alignment offset by precise spacing and subsequent dicing of the insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor dies are arranged one by one on a carrier board and then diced, then chip packages can be formed in batches, but the process becomes time-consuming and complicated with alignment offset issues
Solution Approach 1:
The patent segments the wafer into multiple chips through dicing after the entire wafer undergoes surface treatment and carrier board attachment. This allows batch processing of multiple chips simultaneously while maintaining simplicity in the overall process flow, resolving the contradiction between batch productivity and process complexity.
Solution Approach 2:
The patent applies surface treatment and attaches carrier boards to the entire wafer before dicing into individual chips. This preliminary action enables batch processing of multiple chips at once, improving productivity while keeping the process straightforward by performing all preparatory steps on the complete wafer rather than individual chips.
2Productivity
If semiconductor dies are arranged one by one on a carrier board, then batch packaging is achieved, but alignment offset issues occur
Solution Approach 1:
The patent performs segmentation (dicing) after the entire wafer has been treated and mounted on carrier boards, ensuring that all chips on the wafer maintain consistent alignment relative to the wafer center. This eliminates alignment offset issues while still enabling batch processing of multiple chips.
Solution Approach 2:
The patent merges multiple chips into a single wafer structure for the surface treatment and carrier board attachment steps. By treating all chips together as one unit during critical alignment steps, the patent ensures consistent positioning and eliminates alignment offset problems that would occur with individual chip handling.
3Ease of manufacture
If conventional dicing is performed before packaging, then individual chips are formed, but the process becomes time-consuming and complicated
Solution Approach 1:
The patent performs dicing as a preliminary action after surface treatment and carrier board attachment, but before the final packaging steps. This timing allows the entire wafer to be processed uniformly, simplifying the overall process while enabling efficient batch production that reduces total manufacturing time.
Solution Approach 2:
The patent maintains continuous processing by performing surface treatment, carrier board attachment, and dicing in a continuous sequence on the entire wafer without interrupting to handle individual chips. This continuous batch processing simplifies the manufacturing process and reduces total production time compared to sequential individual chip processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method streamlines the chip packaging process, reducing complexity and eliminating alignment offset issues, thereby enhancing efficiency and accuracy in chip package manufacturing.
Implementation Method 1
heating the first adhesion layer to a first temperature, such that the first carrier board and the first adhesion layer are removed
Implementation Method 2
heating the second adhesion layer to a second temperature, such that the second carrier board and the second adhesion layer are removed
Data Source
AI summary
A method of manufacturing chip package is disclosed. The method includes providing a wafer having a first surface and a second surface, in which the wafer includes conductive bumps disposed on the first surface; thinning the wafer from the second surface toward the first surface; dicing the wafer to form chips, in which each chip has a third surface and a fourth surface, and at least one of the conductive bumps is disposed on the third surface; disposing the chips on a substrate, such that the conductive bumps are disposed between the substrate and the third surface, in which any two adjacent of the chips are spaced apart by a gap ranging from 50 μm to 140 μm; forming an insulating layer filling the gaps and covering the chips; and dicing the insulating layer along each gap to form a plurality of chip packages.