Wafer-Level Chip Package Redistribution Layer Fabrication
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Solution Overview
Problem
The challenge in fabricating wafer-level chip packages is the difficulty in preventing metal residues between chip packages, which leads to defects and water infiltration, making it hard to achieve reliable and cost-effective mass production.
Innovation Solution
A method involving a wafer with conducting pads, recesses, and isolation layers, where a conductive layer and photo-resist layer are formed, and a solder layer is applied, with an adhesive and interfacial layer to enhance bonding and prevent metal residue issues, using spray coating and sputtering techniques to simplify the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electro-deposited photoresist technique is used to complete lithography process of high-density redistribution layer, then wiring density of redistribution layer is improved, but metal residues remain on sides of chip package causing defects and water infiltration
Solution Approach 1:
The patent divides the photoresist application process into separate spray coating steps for different regions (scribe line area vs. chip area), allowing independent control of photoresist deposition to prevent metal residues while maintaining wiring density
Solution Approach 2:
The patent introduces a spray coating process as an intermediary method between photoresist application and electro-deposition, using aerosol technology to achieve uniform coating without the harmful side effects of traditional electro-deposited photoresist technique
2Manufacturing precision
If complicated electro-deposited photoresist technique is applied, then high-density redistribution layer is achieved, but process complexity increases and manufacturing cost rises
Solution Approach 1:
The patent replaces the complex electro-deposited photoresist system with a simpler spray coating mechanical system, eliminating the need for electrochemical processes while achieving the same lithography results
Solution Approach 2:
The patent changes the deposition method parameter from electro-deposition to spray coating, fundamentally altering the process mechanism to reduce complexity while maintaining the ability to create high-density redistribution layers
3Ease of manufacture
If traditional fabrication method is used, then manufacturing process is established, but metal residues cause defects and water infiltration reducing product reliability
Solution Approach 1:
The patent converts the potential harm of metal residues by using spray coating to precisely control photoresist deposition, eliminating the source of metal contamination while maintaining manufacturing efficiency
Solution Approach 2:
The patent applies spray coating technology in advance to prevent metal residue formation before it occurs, creating a protective coating method that inherently prevents the harmful effects of traditional electro-deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents metal residues, enhances the reliability of conductive paths, and reduces manufacturing costs by simplifying the process and improving automation, making it suitable for mass production.
Implementation Method 1
a photo-resist layer is spray coated on the conductive layer
Implementation Method 2
The photo-resist layer is exposed and developed to expose a part of the conductive layer
Implementation Method 3
The method of stripping the photo-resist layer is by spin coating a solvent for the photo-resist layer on the photo-resist layer to dissolve and remove the photo-resist layer
Implementation Method 4
the conductive layer and the interfacial layer are formed by sputtering
Data Source
AI summary
A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.