Wafer Level Chip Package with Sloped Dielectric Risers
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Solution Overview
Problem
Existing wafer level chip packages face issues with stress in solder bonds due to thermal expansion and contraction differences between chips and circuit panels, and the traces on compliant posts are susceptible to fatigue failure.
Innovation Solution
A method involving a substrate with posts and dielectric risers is used, where a first dielectric material is applied to the substrate's front surface and sidewalls, forming sloping surfaces, and electrically conductive traces are extended from contacts to the tips of the risers, allowing for movement and reducing stress concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer level packaging is used to fabricate chip packages before severing, then manufacturing efficiency is improved, but stress management during thermal expansion becomes problematic
Solution Approach 1:
The invention modifies the physical parameters of the connection structure by introducing a compliant post with specific mechanical properties (different from both the chip and circuit panel) and coating it with a dielectric layer. This creates a gradient structure that progressively manages stress through the assembly, enabling wafer-level packaging to maintain reliability under thermal cycling conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reliability of wafer level chip packages by alleviating stress on solder bonds and reducing the likelihood of metal fatigue in conductive lines, thereby improving the assembly's mechanical and electrical stability.
Implementation Method 1
The first dielectric material may be applied in a flowable condition, as, for example, by spin-coating the substrate
Data Source
AI summary
Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.