Wafer-Level Chip Package Manufacturing via Trench Etching
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Solution Overview
Problem
Conventional chip packaging methods are time-consuming and prone to alignment offset issues, making them inefficient and costly.
Innovation Solution
A method involving a wafer with conductive pads and bumps, thinning, forming insulating and passivation layers, and etching trenches to create chip packages, which reduces process duration and eliminates alignment offsets by precise dicing along trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semiconductor dies are arranged on a carrier board and packaged one by one, then packaging can be performed, but the process becomes time-consuming and complicated
Solution Approach 1:
Multiple semiconductor dies are packaged simultaneously on a single carrier board rather than one by one, merging multiple packaging operations into a single batch process. This maintains packaging functionality while dramatically improving manufacturing efficiency and reducing process complexity
Solution Approach 2:
The wafer is divided into multiple semiconductor dies that are arranged in a grid pattern on the carrier board, allowing systematic batch processing. Each die is individually positioned but processed together as a group, combining segmentation with batch manufacturing
2Ease of manufacture
If conventional dicing and packaging methods are used, then chip packages can be formed, but alignment offset issues occur
Solution Approach 1:
Conductive bumps are formed on the semiconductor dies before packaging, and reference marks are established during wafer fabrication. These preliminary structures serve as alignment references during the packaging and dicing processes, ensuring precise positioning and eliminating alignment offset issues
Solution Approach 2:
The patent replaces manual or mechanical alignment methods with a systematic approach using pre-formed conductive bumps and reference marks as alignment features. The bumps serve as both electrical connections and mechanical positioning references, substituting complex mechanical alignment systems
3Volume of moving object
If wafer thickness is reduced through thinning, then chip package size is minimized, but wafer strength decreases
Solution Approach 1:
The wafer is thinned to the desired thickness before the packaging process begins, establishing the final chip package dimensions early. This preliminary thinning allows subsequent packaging steps to proceed without requiring excessive wafer removal, maintaining structural integrity throughout the process
Solution Approach 2:
The packaging process combines multiple operations including thinning, bump formation, and die attachment in a integrated sequence. By combining these steps, the wafer is thinned to minimal thickness while maintaining strength through the supportive carrier board and simultaneous processing
Data Source
AI summary
A method of manufacturing chip package is disclosed. The method includes steps of providing a wafer with an upper surface and a lower surface opposite thereto, in which a plurality of conductive pads are disposed on the upper surface; forming a plurality of conductive bumps on the corresponding conductive pads; thinning the wafer from the lower surface towards the upper surface; forming an insulating layer under the lower surface; etching the upper surface of the wafer to form a plurality of trenches exposing the insulating layer; forming a passivation layer covering an inner wall of each of the trenches; and dicing the passivation layer and the insulating layer along each of the trenches to form a plurality of chip packages.