Wafer Level Chip Packaging Lid Spacing

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Solution Overview

Problem

Current microelectronic packaging methods lack efficiency and reliability in providing protective lids for sensitive devices like optoelectronic and MEMS chips, as existing methods do not effectively space the cap from the chip's active areas, leading to potential damage and contamination.

Innovation Solution

A method involving the assembly of a lid wafer with a device wafer, where the lid wafer is severed into angled lid elements, allowing for the creation of lidded microelectronic elements with a protective cap that is spaced from the chip's active areas, using adhesive application and specific sawing techniques to ensure precise alignment and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a protective lid is placed directly over the chip's active area, then protection is provided, but the lid touches and damages the acoustical or mechanical elements

Engineering Contradiction:
Improveprotection reliabilityVSAvoidphysical damage to active elements
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a vertical spacing dimension by using a dicing lane structure that creates a gap between the lid and the active area. The lid is positioned over the dicing lane rather than directly over the active elements, transforming the protection mechanism from direct contact to indirect protection through spatial separation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The dicing lane acts as an intermediary structure between the lid and the active elements. This intermediate feature provides the necessary physical separation, allowing the lid to protect the chip while preventing direct contact with sensitive acoustical or mechanical elements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If adhesive is applied to cover contacts for bonding, then bonding strength is improved, but contacts become obscured and inaccessible

Engineering Contradiction:
Improvebonding strengthVSAvoidcontact accessibility
Core Design Contradiction:
StrengthVSEase of operation

Solution Approach 1:

The adhesive is applied selectively to specific regions of the lid - primarily to the edges and dicing lane areas - rather than uniformly across the entire surface. This localized application provides sufficient bonding strength while leaving contact regions accessible.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of applying adhesive to all surfaces, the patent uses partial action by limiting adhesive application to only the necessary bonding areas (edges and dicing lanes), achieving adequate bonding strength without obscuring the contacts.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of manufacture

If the lid wafer is severed at right angles to the normal, then manufacturing simplicity is maintained, but edge alignment with supporting walls is poor

Engineering Contradiction:
Improvesevering process simplicityVSAvoidedge alignment precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent employs asymmetric severing where the lid wafer is cut at an angle relative to the normal, creating non-perpendicular edges. This asymmetric approach improves edge alignment with the supporting walls while maintaining reasonable manufacturing complexity through controlled angular cutting.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables efficient and reliable protection of sensitive microelectronic devices by spacing the cap from the active areas, preventing physical and chemical damage while maintaining the integrity of the chip's functionality.

Implementation Method 1

applying an adhesive to at least one of the lid wafer or the device wafer and attaching the lid wafer to the device wafer with the adhesive

Methodology Applied
Scientific EffectAdhesive bonding: Adhesive

Data Source

PatentUS7936062B2Wafer level chip packaging
Publication Date: 2011.05.03 ADEIA SEMICON TECH LLC
  • US7936062B2 patent drawing
  • US7936062B2 patent drawing
  • US7936062B2 patent drawing

AI summary

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.