Wafer-Level Chip Packaging with Transparent Adhesive Layer
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Solution Overview
Problem
Conventional IC packaging processes are prone to voids or bubbles in the adhesive layer, which can contaminate or scratch light-sensing areas on chips, leading to distorted light signals and increased costs.
Innovation Solution
A wafer-level chip packaging process involving the formation of through holes under pads, filling them with conductive material, and using a transparent adhesive layer formed by spin coating to minimize voids and bubbles, ensuring complete encapsulation of the active surface by a transparent cover panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional IC packaging process is used with wire bonding or flip chip bonding followed by encapsulation, then electrical connection between chip contacts and external carriers is achieved, but residual particles can easily fall on the chip and lower process yield
Solution Approach 1:
The patent performs wafer-level packaging operations before chip separation, completing the encapsulation process while chips are still attached to the wafer. This preliminary action prevents particles from contaminating chips during handling and separation processes, thereby improving process yield
Solution Approach 2:
The patent combines multiple packaging operations into a single wafer-level process, integrating electrical connection formation and encapsulation into one unified process flow. This merging eliminates intermediate handling steps that could introduce particle contamination
2Reliability
If a transparent adhesive layer is used to encapsulate the chip, then protection against moisture and heat is provided, but residual voids or bubbles form in the adhesive layer creating gaps
Solution Approach 1:
The patent removes air from the encapsulation cavity before applying the transparent adhesive layer, extracting the harmful gas phase that would otherwise form voids and bubbles. This ensures complete filling of the adhesive material and eliminates gaps that could compromise chip protection
Solution Approach 2:
The patent applies vacuum or pressure control during the adhesive layer formation process to change the physical parameters of the encapsulation environment. This parameter adjustment prevents bubble formation and ensures uniform adhesive distribution, improving manufacturing precision
3Ease of manufacture
If particles are lodged in the gap between transparent cover panel and chip, then the structure is formed, but particles may contaminate or scratch the light-sensing area and cause distorted light signals
Solution Approach 1:
The patent performs particle removal and cleaning operations before final encapsulation, eliminating contaminants before they can reach the light-sensing area. This preliminary cleaning action prevents particle-induced defects while maintaining ease of manufacture
Solution Approach 2:
The patent implements measures to prevent particle contamination from the outset, using cleanroom processing and particle-free handling techniques. This preliminary anti-action protects the light-sensing area before particles can cause contamination or scratching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process significantly reduces residual voids and bubbles in the adhesive layer, protecting the active surface and maintaining the integrity of light signals, thereby enhancing the reliability and yield of chip packaging.
Implementation Method 1
a transparent adhesive layer formed by spin coating to minimize voids and bubbles
Data Source
AI summary
A wafer-level chip packaging process includes the following steps. First, a wafer having a plurality of chip units, an active surface, and a corresponding back surface is provided. Each chip unit has a plurality of pads on the active surface. Next, a plurality of through holes is formed under the pads. The through holes are filled with a conductive material such that the conductive material within each through hole is electrically connected to corresponding one of the pads and a portion of the conductive material is exposed and protrudes from the back surface of the wafer. Thereafter, a transparent adhesive layer is formed on the active surface. Next, a transparent cover panel is disposed on the transparent adhesive layer such that the transparent cover panel is connected to the wafer through the transparent adhesive layer. Afterwards, a singulation step is performed to form a plurality of independent chip package structures.