Wafer Level Chip Scale Package Thermal Warpage Control
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Solution Overview
Problem
Traditional semiconductor packaging methods lead to wafer warpage and device failure due to thermal expansion mismatches between thinner device wafers and thicker backside metals, resulting in cracking and reduced reliability.
Innovation Solution
A semi-wafer level packaging method that involves a dicing process to separate the device layer before attaching a metal supporting structure and a singulation process to singulate the metal structure, including steps like grinding, metallization, tape bonding, and removing tapes to manage thermal stress and maintain device integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thinner device wafer is attached to a thicker backside metal to reduce resistance, then electrical resistance is reduced, but wafer warpage occurs due to thermal expansion mismatch
Solution Approach 1:
The patent applies a dicing process to divide the wafer into individual devices before attaching the metal supporting structure. This segmentation allows each device to be independently packaged with its own metal structure, reducing the cumulative thermal expansion mismatch and preventing wafer-level warpage while maintaining low resistance through direct metal-to-device contact.
Solution Approach 2:
The patent performs the dicing process before attaching the metal supporting structure. This preliminary action separates the devices while they are still on the wafer, allowing subsequent metal attachment to occur on individual devices rather than a full wafer, thereby preventing warpage caused by thermal expansion mismatch across the entire wafer.
2Shape
If a dicing process is applied before attaching metal supporting structure, then wafer warpage is reduced, but process complexity increases
Solution Approach 1:
The patent segments the packaging process into distinct stages: dicing the wafer into individual devices, then attaching metal supporting structures to each device, and finally applying singulation to separate the packaged devices. This segmentation of the process, while adding steps, allows each stage to be optimized independently and prevents warpage by ensuring metal attachment occurs on flat, diced devices rather than a full wafer.
3Reliability
If a thicker backside metal is used, then resistance is reduced, but thermal expansion mismatch with thinner wafer increases causing cracking
Solution Approach 1:
By dicing the wafer into individual devices before metal attachment, the patent reduces the total area over which thermal expansion mismatch occurs. Each individual device experiences less stress from the metal supporting structure than a full thin wafer would, preventing cracking while maintaining the low resistance benefits of thicker metal.
Solution Approach 2:
The patent applies the metal supporting structure locally to each individual device rather than across the entire wafer. This localized approach allows the thicker metal to be used effectively for reducing resistance at each device level while the overall wafer structure remains intact and free from warpage-induced cracking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces wafer warpage, minimizes resistance, and enhances device reliability by effectively managing thermal expansion and maintaining the structural integrity of semiconductor packages.
Implementation Method 1
grinding a back side of the wafer
Implementation Method 2
bonding a supporting structure
Data Source
AI summary
A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.