Wafer Level Chip Scale Package System with Stress Relieving Encapsulant
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Solution Overview
Problem
Current integrated circuit packaging methods, such as flip chip attachment, face challenges in miniaturization, high costs, and process difficulties, particularly with the alignment of smaller ball grid arrays and the risk of damage during under-filling, which hinder the development of smaller and more intelligent electronic devices.
Innovation Solution
A wafer level chip scale package system is introduced, where a first integrated circuit is placed over a semiconductor wafer with a second integrated circuit, connected via a second electrical interconnect, and a stress relieving encapsulant is formed around the perimeter to cover the interconnect, allowing for singulation of chip scale packages from the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ball grid array technology uses smaller balls with tighter pitch to achieve miniaturization, then packaging density is improved, but alignment precision between conductive bumps and bond pads deteriorates
Solution Approach 1:
A metal redistribution layer (RDL) is introduced as an intermediate layer on the surface of the bottom die. This RDL acts as a mediator that receives conductive bumps from the flip chip die and redistributes connections to bond pads, enabling alignment tolerance and solving the alignment precision problem while maintaining high packaging density
Solution Approach 2:
The electrical connection function is segmented into two separate components: the conductive bumps for mechanical and electrical attachment, and the metal redistribution layer for signal routing. This segmentation allows independent optimization of bump pitch for density and RDL pattern for alignment tolerance
2Productivity
If flip chip mounting is used to achieve improved electrical performance and packaging density, then productivity is improved, but device complexity increases due to requirement of specialized mounting devices
Solution Approach 1:
The manufacturing process is segmented into standard semiconductor fabrication steps (photolithography, etching, deposition) for creating the RDL and attachment to conventional processing, separating the complex flip chip mounting from the standard fabrication flow
Solution Approach 2:
The metal redistribution layer is fabricated in advance during standard semiconductor processing before the flip chip attachment step, preparing the connection infrastructure beforehand and enabling simpler, more conventional mounting operations
3Reliability
If under-fill process is used to mechanically couple the BGA component to the carrier substrate, then reliability is improved, but harmful factors increase due to risk of damage to the active surface of the bottom die
Solution Approach 1:
The metal redistribution layer serves as an intermediary structure that provides both electrical connection and mechanical support. By distributing mechanical loads across the RDL and underlying die structure rather than concentrating forces at bump-die interfaces, the RDL reduces stress on the active surface during under-fill processing
Data Source
AI summary
A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.