Wafer-Level Computing Board Cooling and Power Delivery
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Solution Overview
Problem
Conventional von Neumann architecture faces limitations in memory and communication bandwidth, particularly in processing large amounts of unstructured data, due to the bottleneck between the CPU and memory.
Innovation Solution
A stacked multi-wafer structure with embedded Simple Specialized Processors (SSPs) in a large sea of computer memory, where SSPs perform memory-intensive operations and transmit high-level results to General Management Processors (GMPs), alleviating bandwidth burdens and enabling efficient power and data communication through specialized wiring and interconnectivity schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional von Neumann architecture is used with separated CPU and memory, then the system structure is simple and easy to manufacture, but the memory and communication bandwidth is limited due to the bottleneck between CPU and memory
Solution Approach 1:
The system is divided into multiple independent wafer layers, each containing specialized processing units (SSPs) and memory devices. This segmentation allows parallel processing operations to occur simultaneously across different layers, dramatically increasing memory and communication bandwidth while distributing the computational workload to reduce the bottleneck effect inherent in conventional von Neumann architectures.
Solution Approach 2:
The patent transitions from a two-dimensional planar architecture to a three-dimensional stacked wafer structure. By stacking multiple processing and memory wafers vertically, the system achieves higher bandwidth and throughput without proportionally increasing the footprint area, effectively adding a vertical dimension to expand system capacity and communication pathways.
2Productivity
If multiple wafer layers are stacked to increase processing capacity, then memory and communication bandwidth improve, but power delivery and thermal management become more difficult
Solution Approach 1:
The retainer elements serve multiple functions simultaneously: they mechanically secure the wafer stack, provide electrical power delivery through integrated contacts, and facilitate thermal management through heat dissipation pathways. This multi-functionality reduces the need for separate dedicated components for each function, simplifying the overall power delivery system while maintaining high processing capacity across multiple wafer layers.
Solution Approach 2:
The retainer elements act as intermediary components between the power source and the multiple wafer layers. They provide a standardized interface that distributes power to each layer while managing the electrical connections, thereby simplifying power delivery to the complex multi-wafer structure and enabling scalable processing capacity without proportionally increasing power delivery complexity.
3Productivity
If multiple wafer layers are stacked to increase processing capacity, then memory and communication bandwidth improve, but thermal management becomes more difficult
Solution Approach 1:
The retainer elements serve multiple functions simultaneously: they mechanically secure the wafer stack, provide electrical power delivery through integrated contacts, and facilitate thermal management through heat dissipation pathways. This multi-functionality reduces the need for separate dedicated components for each function, simplifying the overall power delivery system while maintaining high processing capacity across multiple wafer layers.
Solution Approach 2:
The retainer elements act as intermediary components between the power source and the multiple wafer layers. They provide a standardized interface that distributes power to each layer while managing the electrical connections, thereby simplifying power delivery to the complex multi-wafer structure and enabling scalable processing capacity without proportionally increasing power delivery complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively manages memory and communication bandwidth by distributing processing across multiple SSPs, reducing the burden on conventional CPU memory bandwidth and enabling efficient power and data transfer within the cortical system.
Implementation Method 1
a holding device that mates with the retainer elements to provide power to the retaining elements, the holding device including wire springs that contact either the top layer or a bottom layer of the wafer
Implementation Method 2
two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer
Data Source
AI summary
A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.