Wafer-Level Contact Pads with Passivation-Defined Openings
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Solution Overview
Problem
Integrated circuits face challenges in coupling discrete passive components due to space constraints on printed circuit boards (PCBs) and parasitic effects, which affect performance and yield.
Innovation Solution
Components are placed on the active side of a wafer with contact pads formed on a stack of materials, including passivation-defined layers to reduce short circuits and parasitic capacitance, allowing for improved electrical coupling and reduced PCB size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete passive components are coupled to a PCB and IC through conductive traces, then electrical coupling is achieved, but PCB space is consumed and parasitic effects increase
Solution Approach 1:
The patent merges the IC substrate and passive components into a single integrated structure. The IC is formed on a substrate with discrete passive components fabricated directly on the same substrate, eliminating the need for separate PCB mounting and trace routing. This integration directly reduces PCB space consumption while maintaining electrical coupling quality.
Solution Approach 2:
The patent transitions from a two-dimensional PCB layout to a three-dimensional integrated structure. Multiple conductive layers are stacked vertically on the substrate, with conductive traces routing signals through different layers. This vertical dimensionality allows compact component placement and reduces the horizontal footprint on the PCB.
2Reliability
If discrete passive components are coupled to a PCB and IC through conductive traces, then electrical coupling is achieved, but parasitic capacitance increases reducing performance
Solution Approach 1:
The patent merges the IC substrate and passive components into a single integrated structure. The IC is formed on a substrate with discrete passive components fabricated directly on the same substrate, eliminating the need for separate PCB mounting and trace routing. This integration directly reduces PCB space consumption while maintaining electrical coupling quality.
Solution Approach 2:
The patent extracts the passive components from the traditional PCB environment and relocates them directly onto the IC substrate. By taking out the components from the PCB trace environment (which generates parasitic capacitance) and placing them in direct contact with IC pads on the substrate, the harmful parasitic effects are minimized.
3Ease of manufacture
If contact pads are formed without passivation-defined openings, then manufacturing is simpler, but short circuits and underfills occur reducing yield
Solution Approach 1:
The patent introduces a passivation layer as an intermediary between the conductive contact pads and the external environment. This passivation layer with defined openings acts as a mediator that provides mechanical support, defines precise contact pad boundaries, and prevents short circuits while allowing controlled electrical connections. The intermediary structure resolves the conflict between manufacturing simplicity and yield reliability.
4Quantity of substance
If component size is reduced to fit more on PCB, then device density increases, but parasitic effects increase proportionally
Solution Approach 1:
The patent merges the IC substrate and passive components into a single integrated structure. The IC is formed on a substrate with discrete passive components fabricated directly on the same substrate, eliminating the need for separate PCB mounting and trace routing. This integration directly reduces PCB space consumption while maintaining electrical coupling quality.
Solution Approach 2:
The patent transitions from a two-dimensional PCB layout to a three-dimensional integrated structure. Multiple conductive layers are stacked vertically on the substrate, with conductive traces routing signals through different layers. This vertical dimensionality allows compact component placement and reduces the horizontal footprint on the PCB.
Data Source
AI summary
Components may be placed on an active side of a wafer as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer may be passivation-defined by forming a conductive terminal over a first dielectric layer and a forming a passivating, second dielectric layer over the conductive terminal. Openings formed in the second dielectric layer define component contacts to the conductive terminal and circuitry on the wafer coupled to the conductive terminal. Trenches may be used between pairs of contact pads to further reduce issues resulting from short circuits and/or underfills. A conductive pad may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer.