Wafer Level IC Assembly Using Pre-Soldered Copper Posts

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Solution Overview

Problem

Conventional wafer-level packaging methods, such as copper-to-copper post bonding, are time-consuming and costly due to high temperature requirements and the risk of wafer breakage from compression, with no standard industry method and high yield loss from misalignment.

Innovation Solution

The method involves forming pre-solder on a mother device wafer with copper posts, aligning and reflowing it to bond with dies, using a reducing atmosphere or underfill material with a reducing agent to lower bonding temperatures and eliminate compression, thereby reducing processing time and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional copper-to-copper post bonding with thermal bonding technology is used, then reliable electrical connection is achieved, but processing time becomes extremely long (20-30 seconds per die) and manufacturing cost increases

Engineering Contradiction:
Improvebonding reliabilityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention changes the bonding temperature parameter from above copper's melting point (>1000°C) to a lower temperature range (200-400°C) by using solder as an intermediate bonding material. This parameter change enables significantly faster processing while maintaining bonding reliability through the eutectic reaction of solder at lower temperatures.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention introduces solder as an intermediary bonding material between the copper posts of the mother device wafer and the copper posts of the dies. This intermediary material enables bonding at lower temperatures and shorter times, resolving the contradiction between reliable connection and processing efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If high temperature thermal bonding is used to bond copper posts, then strong bonding is achieved, but wafer breakage occurs due to compression and high yield loss results from misalignment

Engineering Contradiction:
Improvebond strengthVSAvoidwafer integrity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The invention changes the temperature parameter from >1000°C to 200-400°C, eliminating the need for high compression forces that cause wafer breakage. The solder's eutectic reaction provides sufficient bond strength at these lower temperatures without compromising wafer integrity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If conventional copper-to-copper post bonding equipment is used, then bonding is achieved, but equipment complexity and manufacturing cost become very high

Engineering Contradiction:
Improvebonding qualityVSAvoidequipment complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention changes the bonding temperature to a lower range (200-400°C) that can be achieved with simpler, more cost-effective equipment. This eliminates the need for extremely high-temperature bonding equipment while maintaining bonding quality through solder's eutectic reaction.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly decreases processing time, reduces manufacturing costs, and minimizes wafer breakage and yield loss by using pre-formed solder to bond copper posts at lower temperatures without compression, improving overall efficiency and yield.

Implementation Method 1

The copper posts 12 and 13 are bonded together in an environment of a temperature higher than the melting point of copper by solid state diffusion

Methodology Applied
Scientific EffectSolid state diffusion: Diffusion

Implementation Method 2

The solder is preferably reflowed in an atmosphere having a reducing agent like hydrogen, so that the solder is reduced in the reflowing process to bond the first and second posts

Methodology Applied
Scientific EffectReduction: Reduction

Data Source

PatentUS8247267B2Wafer level IC assembly method
Publication Date: 2012.08.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8247267B2 patent drawing
  • US8247267B2 patent drawing
  • US8247267B2 patent drawing

AI summary

A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.