Wafer-Level Crackstop Testing Using Tensioned Layers

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Solution Overview

Problem

Current methods lack efficient means to determine the effectiveness of crackstop structures in semiconductor wafer assemblies, which can weaken due to design or material issues, leading to ineffective crack propagation arrest during stress testing, and there is a need for a method to assess BEOL integrity at the wafer level in a time and resource-efficient manner.

Innovation Solution

A method involving the use of a tensioned layer with internal tensile forces oriented in horizontal directions is applied to prototype wafer assemblies, where laser scribing initiates and propagates horizontal cracks, allowing for the evaluation of crackstop structure designs without modifying existing BEOL layers, and the tensioned layer is patterned to accelerate crack propagation within the BEOL layers for testing purposes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If laser scribing is performed on wafer level semiconductor assemblies to initiate and propagate cracks for testing, then crack propagation can be observed to evaluate crackstop structure designs, but the process requires additional time and resources for qualification testing

Engineering Contradiction:
Improvecrackstop structure effectivenessVSAvoidqualification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by introducing a tensioned layer with internal tensile forces before performing laser scribing. This pre-conditioning of the wafer assembly accelerates crack propagation during subsequent laser scribing, enabling faster evaluation of crackstop structure designs without compromising reliability assessment

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the physical parameters of the wafer assembly by adding a tensioned layer that modifies the stress state. This parameter change (introducing internal tensile forces) accelerates crack propagation kinetics, reducing the time required for qualification testing while maintaining the ability to assess crackstop effectiveness

Inventive Principle:
Principle #35Parameter changes

2Productivity

If conventional testing methods are used to assess crackstop robustness, then existing BEOL layers remain unmodified, but the testing process is inefficient and time-consuming

Engineering Contradiction:
Improvetesting efficiencyVSAvoidwafer assembly structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a tensioned layer as an intermediary element that facilitates accelerated crack propagation during testing. This intermediary layer with internal tensile forces acts as a mediator between the laser scribing process and the crackstop structures, enabling faster testing while keeping modifications to existing BEOL layers minimal

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The tensioned layer is applied selectively to specific regions of the wafer assembly where crack propagation acceleration is needed for testing purposes. This local application approach improves testing efficiency without unnecessarily complicating the entire wafer assembly structure

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables accelerated determination of crackstop robustness and BEOL integrity at the wafer level, reducing qualification time and costs by simulating packaging stress conditions, allowing for early identification of weak designs and preventing defective chip assembly, thereby improving the reliability of semiconductor chip assemblies.

Implementation Method 1

a tensioned layer located on top of the metallization layer, with the tensioned layer being made of material having internal tensile forces oriented in the horizontal directions

Methodology Applied
Scientific EffectTensile stress: Tension

Implementation Method 2

the wafer undergoes laser scribing which introduces and/or propagates vertical and horizontal cracks

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS9947598B1Determining crackstop strength of integrated circuit assembly at the wafer level
Publication Date: 2018.04.17 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9947598B1 patent drawing
  • US9947598B1 patent drawing
  • US9947598B1 patent drawing

AI summary

A methodology and associated wafer level assembly of testing crackstop structure designs. The wafer level semiconductor assembly includes: a substrate structure shaped to define a set of horizontal directions; a metallization layer located on top of the substrate structure, with the metallization layer including a crackstop structure formed therein in accordance with a crackstop structure design; and a tensioned layer located on top of the metallization layer, with the tensioned layer being made of material having internal tensile forces oriented in the horizontal directions. The tensile forces promote horizontal direction crack propagation in the metallization layer so that the crackstop structure design can be tested more rigorously and reliably before deciding on the crackstop design structure to put into mass production (which mass produced product would typically not include the tensioned layer).