Wafer-Level Chip Scale Package Manufacturing
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Solution Overview
Problem
Chip scale packages (CSPs) are currently high in cost due to conventional manufacturing methods, which hinders their widespread adoption for miniaturized electronic devices.
Innovation Solution
A method for manufacturing CSPs at the wafer level using an anisotropic conductive adhesive layer to attach a patterned circuit layer to a semiconductor chip, with metal bumps formed through solder-ball placement or stencil printing, allowing for mass production and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional manufacturing methods are used for chip scale packages, then the package can be produced with standard processes, but the cost per unit becomes high
Solution Approach 1:
The patent combines multiple manufacturing operations into a single wafer-level process. The patterned circuit layer is attached to multiple semiconductor chips simultaneously on a wafer, and metal bumps are formed on all contact pads in one batch. This merging of operations into a parallel wafer-level process significantly reduces the cost per unit while maintaining manufacturability
Solution Approach 2:
The patterned circuit layer serves multiple functions simultaneously: it provides electrical connection through contact pads, structural support for metal bumps, and a platform for wafer-level assembly. This multi-functionality reduces the number of separate components and processes needed, thereby reducing overall manufacturing cost
2Productivity
If wafer-level manufacturing is implemented, then mass production efficiency increases, but process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct modular steps: (1) forming the anisotropic conductive adhesive layer, (2) attaching the patterned circuit layer to the wafer, (3) forming metal bumps on contact pads, and (4) dicing into individual packages. This segmentation allows each step to be optimized independently while maintaining overall wafer-level productivity
Solution Approach 2:
The anisotropic conductive adhesive layer acts as an intermediary that enables electrical connection between the patterned circuit layer and semiconductor chips without requiring direct metal-to-silicon bonding. This intermediary layer simplifies the attachment process and enables wafer-level manufacturing by providing a reliable, low-complexity bonding mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the mass production of CSPs at a lower cost, reducing board real estate requirements and maintaining high I/O count and thermal path efficiency while lowering production expenses.
Implementation Method 1
an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip
Implementation Method 2
A plurality of metal bumps are respectively disposed in the openings of the patterned circuit layer and mounted to the exposed portions of the contact pads of the patterned circuit layer for making external electrical connection
Data Source
AI summary
A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.