Wafer-Level Microelectronic Die Stacking Packaging
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Solution Overview
Problem
Conventional microelectronic device stacking processes are costly, complex, and result in high footprints and vertical space occupation due to multiple steps and rigorous packaging processes, leading to potential damage and discarding of entire devices if individual dies become inoperable.
Innovation Solution
Wafer-level packaging method involving releasably attaching known good microelectronic dies to a carrier substrate, stacking, encapsulating, and then separating them, with electrical couplers attached after carrier removal, ensuring only functional dies are used and reducing the number of packaging steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stacking processes are used with multiple packaging steps, then devices can be assembled, but the process becomes costly and complex with reduced throughput
Solution Approach 1:
The patent combines multiple separate packaging steps (die attachment, wire bonding, encapsulation, singulation) into a single integrated wafer-level process where all operations are performed on the wafer before singulation, eliminating the need for separate handling and processing of individual dies
Solution Approach 2:
The patent performs all packaging operations (attachment, bonding, encapsulation) in advance while the dies are still on the wafer, before the final singulation step. This preliminary action eliminates the need for subsequent handling and processing of individual dies, reducing complexity and cost
2Reliability
If conventional stacking processes with interposer substrate are used, then devices can be mounted, but the footprint and vertical space occupation increase
Solution Approach 1:
The patent extracts and eliminates the interposer substrate from the packaging structure, directly mounting the stacked dies to the target substrate. This removal of the intermediate layer reduces both the footprint and vertical profile of the final device assembly
Solution Approach 2:
The patent transitions from a planar packaging approach requiring large footprint for interposer and ball-grid arrays to a vertical stacking approach where multiple dies are stacked in the Z-dimension, achieving higher component density within a smaller footprint
3Measurement precision
If dies are tested before singulation, then functional dies can be identified, but rigorous packaging processes after testing can still cause damage
Solution Approach 1:
The patent performs die testing before singulation and then immediately proceeds with all subsequent packaging operations (attachment, bonding, encapsulation) while the dies are still protected on the wafer. The encapsulation is performed before singulation, providing continuous protection throughout the process
Solution Approach 2:
The patent applies encapsulant material before singulation to create a protective cushion around the dies during subsequent handling and processing steps, preventing damage to the dies while maintaining their functional status
4Reliability
If multiple separate packaging steps are used, then devices can be assembled, but throughput is reduced
Solution Approach 1:
The patent merges multiple sequential packaging operations into a single parallel wafer-level process, where all dies on the wafer undergo attachment, bonding, and encapsulation simultaneously in one processing cycle, dramatically increasing throughput
Solution Approach 2:
The patent maintains continuous processing by performing all packaging operations on the wafer without breaking the process flow or requiring intermediate handling of individual dies, eliminating idle time and maximizing productivity
Data Source
AI summary
Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.