Wafer-Level Encapsulated Semiconductor Device with CTE-Matched Carrier
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wafer-level chip-scale packaging of CMOS image sensors faces challenges such as delamination due to mismatched coefficients of thermal expansion (CTE) between conductive pads, spacer elements, and epoxy sealants, and limited cavity height which affects the precision of microlens placement and increases production costs.
Innovation Solution
The use of a carrier wafer with a CTE matched to silicon, combined with a spacer wafer that forms dams to create sealed cavities around microlens arrays, eliminating the need for bridging sealants and allowing for increased cavity heights through precise etching and alignment techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epoxy sealant is used to bridge the cavity between packaging layer and substrate, then the cavity is sealed, but delamination occurs due to mismatched coefficients of thermal expansion
Solution Approach 1:
The patent removes the epoxy sealant bridging function entirely by using recesses in the carrier wafer to form the cavity enclosure. The sealant is only applied at peripheral edges, not bridging the cavity height, thereby eliminating the thermal expansion mismatch problem while maintaining sealing functionality.
Solution Approach 2:
The recesses in the carrier wafer act as an intermediary structure that encloses the cavity without requiring bridging sealant. This intermediate geometric feature provides both cavity definition and structural support, eliminating the need for problematic epoxy bridges.
2Illumination intensity
If carrier wafer is made optically transparent, then light transmission is maintained, but contaminates can still reach microlenses
Solution Approach 1:
The cavity formed by recesses in the carrier wafer creates a nested protective structure around the microlens array. The microlenses are enclosed within the cavity while the carrier wafer remains optically transparent, allowing light transmission while preventing contaminate access.
3Manufacturing precision
If cavity height is increased, then microlens placement precision is improved, but production cost increases
Solution Approach 1:
The patent enables precise control of cavity height through the depth of recesses formed in the carrier wafer. By adjusting the recess depth parameter, optimal cavity heights for microlens placement can be achieved without requiring complex additional structures, thereby maintaining manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces delamination risks, maintains optical quality, and enables larger cavity heights, improving image sensor performance by precisely placing microlens arrays at the focal plane, while ensuring chemical resistance and thermal stability.
Implementation Method 1
A carrier wafer with a CTE matched to silicon
Implementation Method 2
Recesses 316 are photolithographically etched into carrier wafer 324
Implementation Method 3
a first sealant portion for attaching the dam to the device die
Data Source
AI summary
An encapsulated semiconductor device includes a device die with a semiconductor device fabricated thereon. A carrier layer opposite the device die covers the semiconductor device. A dam supports the carrier layer above the device die, the dam being located therebetween. The semiconductor device further includes a first sealant portion for attaching the dam to the device die, and a means for attaching the dam to the carrier layer. The device die, the dam, and the carrier layer form a sealed cavity enclosing the semiconductor device.A method of encapsulating semiconductor devices formed on a device wafer includes forming an assembly including a carrier wafer and a plurality of dams thereon. After the step of forming, the method attaches the plurality of dams to the device wafer to form a respective plurality of encapsulated semiconductor devices.