Wafer-Level Chip-Scale Filter Packaging Using Through-Wafer Vias
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Solution Overview
Problem
Current packaging technologies for semiconductor and microelectromechanical system devices, such as SAW and BAW filters, require separate formation on semiconductor and piezoelectric substrates, leading to increased size, complexity, and cost, as well as mechanical stress and handling issues with fragile wafers.
Innovation Solution
A wafer-level chip-scale package design that bonds a semiconductor substrate with passive devices to a piezoelectric substrate containing RF filters, using through-wafer vias for electrical connection and a metal seal ring for hermetic sealing, allowing for a single package with reduced size and enhanced mechanical integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate packaging is used for semiconductor devices and piezoelectric filter elements, then each device can be optimized independently, but the overall package size and complexity increase
Solution Approach 1:
The patent merges the semiconductor substrate and piezoelectric substrate into a single integrated package structure. The semiconductor substrate containing passive devices is bonded to the piezoelectric substrate containing the RF filter, creating a unified package that reduces overall complexity while maintaining independent device optimization capabilities through the bonded interface.
2Ease of manufacture
If separate packaging is used for semiconductor and piezoelectric substrates, then manufacturing processes can be optimized independently, but production costs and time increase
Solution Approach 1:
The patent implements preliminary actions by forming cavities, through-wafer vias, and bonding structures on both substrates before final assembly. The semiconductor substrate is prepared with cavities and passive devices, while the piezoelectric substrate is prepared with RF filters, allowing parallel processing and independent optimization of manufacturing processes before the bonding step unifies the structures.
3Reliability
If through-wafer vias are used for electrical connection, then connection impedance is reduced, but mechanical stress on the substrates increases
Solution Approach 1:
The patent uses nested structures where cavities are formed within the substrates and through-wafer vias are embedded within these cavities. The vias are positioned and formed within the substrate thickness, creating a nested configuration that provides low-impedance electrical paths while the cavity structures help distribute and reduce mechanical stress concentrations.
4Reliability
If a hermetic seal is implemented, then package reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs a seal ring structure that is integrated with the substrate assembly. The hermetic seal is achieved through a dedicated seal ring component that is bonded to the substrates, allowing the sealing function to be separated from the main structural elements. This approach simplifies the overall manufacturing by making the sealing function modular and replaceable without affecting the core device structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the integration of semiconductor and acoustic wave elements in a single package, reducing size and production costs, while providing low impedance and low inductance connections, and minimizing mechanical stress and handling challenges, making it compatible with existing GaAs HBT technologies.
Implementation Method 1
a piezoelectric substrate bonded to the semiconductor substrate and has a radio frequency (RF) filter formed thereon, wherein the RF filter is disposed within the cavity defined in the semiconductor substrate
Data Source
AI summary
A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.