Wafer-Level Flat No-Lead Semiconductor Packages

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Solution Overview

Problem

Conventional semiconductor packages require individual construction and involve complex processes like die bonding, wire bonding, and overmolding, which can be inefficient and prone to environmental and thermal hazards.

Innovation Solution

A method involving a substrate with pads for bonding semiconductor dies, followed by overmolding and substrate removal to form wafer-level semiconductor packages, allowing for efficient production and thermal protection without leads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional semiconductor packages are constructed one at a time using die bonding, wire bonding, and overmolding, then each package receives individual protection, but the manufacturing process becomes complex and inefficient

Engineering Contradiction:
Improveprotection qualityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple semiconductor dies are bonded simultaneously to a single substrate in a wafer-level process, combining what would traditionally be separate individual packaging operations into one integrated manufacturing step, thereby reducing overall process complexity while maintaining protection quality

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The substrate is prepared in advance with multiple pads and bonding structures before the dies are attached, allowing subsequent bonding and overmolding operations to proceed efficiently in a single batch process rather than requiring sequential individual package construction

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If individual die bonding and wire bonding are performed for each package, then precise electrical connections are achieved, but production time increases and efficiency decreases

Engineering Contradiction:
Improveelectrical connection precisionVSAvoidproduction efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

Multiple semiconductor dies are bonded to the substrate simultaneously in a wafer-level process, and subsequent overmolding is performed on all packages at once, dramatically increasing production efficiency while maintaining precise electrical connections through the pad-bond wire structure

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The substrate is divided into multiple discrete pad regions, each corresponding to a specific die bond wire connection point, allowing precise electrical connections to be established for each die while enabling batch processing of multiple packages simultaneously

Inventive Principle:
Principle #1Segmentation

3Object-affected harmful factors

If conventional packaging processes are used with multiple processing steps, then environmental and thermal protection is provided, but the process becomes prone to hazards and requires more time

Engineering Contradiction:
Improveenvironmental and thermal protectionVSAvoidmanufacturing cycle time
Core Design Contradiction:
Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The substrate is pre-configured with bonding pads and structural features before die attachment, and overmolding is performed immediately after bonding in a continuous process, reducing the time packages are exposed to environmental hazards during manufacturing while maintaining protective encapsulation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Multiple protection functions (die attachment, electrical connection, and environmental encapsulation) are combined into a single integrated wafer-level packaging process that completes all protective measures in one batch operation, minimizing exposure time to harmful factors

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the mass production of semiconductor packages with improved thermal and environmental protection, reducing complexity and enhancing efficiency in the packaging process.

Implementation Method 1

applying die attach material to the plurality of pads... bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material

Methodology Applied
Scientific EffectPolymerization: Photopolymerisation

Data Source

PatentUS10770333B2Wafer level flat no-lead semiconductor packages and methods of manufacture
Publication Date: 2020.09.08 SEMICON COMPONENTS IND LLC
  • US10770333B2 patent drawing
  • US10770333B2 patent drawing
  • US10770333B2 patent drawing

AI summary

Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.