Wafer-Level Flip Chip Package Without Leadframe
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Solution Overview
Problem
Conventional semiconductor packages require leadframes for packaging, which add expense and complexity, and necessitate additional processing for wettable flanks, whereas leadless packages eliminate the need for leadframes and achieve improved wettable sidewalls for surface mount processing.
Innovation Solution
The method involves wafer-level assembly, including molding, printing of lead terminals, and sawing, without using a leadframe, allowing for exposed lead terminal side walls and eliminating the need for plating on oxidation-resistant materials like silver or gold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional leadframe packaging is used, then mechanical support and lead terminals are provided, but packaging cost and device complexity increase
Solution Approach 1:
The patent extracts and removes the leadframe component from the packaging structure, replacing it with lead terminals directly formed on the substrate. This eliminates the need for separate leadframe materials and assembly steps, directly reducing packaging cost and structural complexity while maintaining the essential function of providing electrical connections.
Solution Approach 2:
The patent merges the lead terminal function with the substrate by directly forming conductive traces and terminals on the substrate surface. This integration eliminates the need for separate leadframe components and their associated assembly processes, thereby reducing both packaging cost and device complexity.
2Ease of manufacture
If conventional QFN packages are used, then compact footprint is achieved, but wettable flanks require additional processing
Solution Approach 1:
The patent extracts the wettable flank processing requirement by forming lead terminals with exposed vertical sidewalls that are inherently wettable during SMT processing. This eliminates the need for additional wettable flank formation steps while maintaining compact package footprint.
Solution Approach 2:
The patent performs preliminary action by forming the lead terminal structure with exposed vertical sidewalls during the substrate fabrication process itself, before packaging assembly. This preliminary structuring ensures inherent wettability during SMT processing without requiring subsequent wettable flank formation steps.
3Reliability
If oxidation resistant materials like silver or gold are used for lead terminals, then corrosion resistance is improved, but plating is required for copper terminals
Solution Approach 1:
The patent extracts the plating process requirement by directly forming lead terminals from oxidation-resistant materials such as silver or gold during substrate fabrication. This eliminates the need for subsequent plating processes while ensuring inherent corrosion resistance and maintaining manufacturing simplicity.
Data Source
AI summary
A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.