Wafer-Level Flipped Die Stacks with Leadframe Interconnects
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Solution Overview
Problem
Conventional stacked microelectronic packages face challenges with complexity, cost, thickness, and testability, particularly in incorporating multiple chips for memory applications like flash memory, requiring improved reliability, thinness, and economical manufacturing.
Innovation Solution
A stacked microelectronic assembly design featuring encapsulated packages with parallel planes, electrically conductive package contacts, and leadframe interconnects, where the encapsulation region contacts edge surfaces and extends to remote surfaces, allowing for efficient electrical coupling and potential inclusion of a heat spreader, with adhesive and dielectric materials for mechanical reinforcement and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple semiconductor chips are stacked within a package to save space, then the surface area occupied by the package is reduced, but the package complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacking by orienting multiple semiconductor chips vertically with their active surfaces facing the same direction. This dimensional change allows multiple chips to occupy a small footprint area while maintaining individual chip functionality and simplifying interconnect architecture compared to conventional stacked packages.
Solution Approach 2:
The support element serves multiple functions simultaneously: it provides mechanical support for the stacked chips, establishes electrical interconnections between chips through conductive vias, and enables thermal management. This multi-functionality reduces the need for additional separate components, thereby reducing overall package complexity.
2Area of stationary object
If conventional stacked packages are used to reduce surface area, then space is saved, but the package thickness increases
Solution Approach 1:
The patent employs thin-film encapsulation layers and sleek packaging materials that provide necessary protection while minimizing thickness. The support element with integrated conductive vias eliminates the need for thick wire bonds or lead frames, thereby reducing overall package thickness while maintaining mechanical integrity and electrical connectivity.
Solution Approach 2:
By stacking chips vertically with minimal spacing and using planar interconnect structures on the support element, the design achieves high integration density in the vertical dimension while keeping each individual layer thin, thus reducing total package thickness compared to conventional approaches.
3Quantity of substance
If multiple chips are stacked in conventional packages, then storage density is improved, but testability and reliability decrease
Solution Approach 1:
The patent segments the testing and validation process into modular stages: individual chip testing before stacking, intermediate testing of stacked assemblies, and final package testing. The support element's conductive vias are structured to enable selective electrical access to specific chips during testing, improving testability while maintaining high storage density through vertical stacking.
Solution Approach 2:
The support element acts as an intermediary structure that facilitates reliable electrical connections between stacked chips through precisely aligned conductive vias. This mediator structure ensures signal integrity and reduces variability in electrical performance, thereby improving overall package reliability and consistency across multiple stacked chips.
4Productivity
If conventional stacked packages are manufactured, then production capacity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent performs preliminary actions by pre-testing and characterizing individual semiconductor chips before stacking, and by pre-forming the support element with conductive via structures. This preliminary preparation enables faster assembly processes and reduces rework, thereby lowering manufacturing costs while maintaining high production capacity through standardized stacking procedures.
Solution Approach 2:
The patent merges multiple manufacturing operations into integrated process steps: the support element fabrication combines substrate preparation, conductive via formation, and interconnect patterning in a single manufacturing flow. This consolidation reduces the number of separate processing steps, decreases manufacturing complexity, and lowers overall production costs while maintaining high throughput capacity.
Data Source
AI summary
An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.