Wafer-Level Grinding for Thin Chip-on-Chip Devices

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for producing thin semiconductor devices with a chip-on-chip structure face limitations in reducing overall thickness while maintaining sufficient strength, as grinding techniques can lead to cracking or breakage.

Innovation Solution

A production method involving wafer preparation, bonding of semiconductor chips, grinding of rear surfaces, resin filling, and controlled wafer grinding to achieve thinning while stabilizing the wafer on a chuck table, followed by division along predetermined lines to produce devices with reduced thickness and minimized damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If semiconductor chips are ground thinner by a grinding device, then the overall thickness of the chip-on-chip structure is reduced, but the strength of the semiconductor chips decreases leading to cracking or breakage

Engineering Contradiction:
Improvethickness of semiconductor deviceVSAvoidstrength of semiconductor chip
Core Design Contradiction:
Length of moving objectVSStrength

Solution Approach 1:

The patent applies preliminary action by performing wafer-level grinding before chip separation. The entire wafer is thinned to the target thickness while chips are still bonded to the wafer, providing structural support during the grinding process. This prevents individual chips from cracking or breaking that would occur if they were ground separately after separation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges multiple chips into a wafer structure for simultaneous processing. By keeping chips bonded to the wafer substrate during grinding, the wafer acts as a unified structure that distributes mechanical stresses, allowing all chips to be thinned together without individual chips suffering from strength deficiencies.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If multiple semiconductor chips are stacked and bonded to reduce overall thickness, then device integration is improved, but the complexity of the production process increases

Engineering Contradiction:
Improvedevice integration efficiencyVSAvoidproduction process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions at the wafer level including chip bonding, alignment, and grinding before separation. By completing these complex operations while chips are still on the wafer substrate, the process is more manageable and precise than attempting to handle and process individual thin chips separately.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the production process into distinct stages: wafer preparation and chip bonding, wafer-level grinding and thinning, resin filling, and final chip separation. This segmentation allows each stage to be optimized independently, reducing overall process complexity despite the multi-step nature of chip-on-chip manufacturing.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If the wafer is ground while held by the chuck table, then grinding precision is improved, but warping of the wafer occurs due to insufficient support

Engineering Contradiction:
Improvegrinding precisionVSAvoidwafer warping
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by providing differential support to the wafer during grinding. The chuck table provides localized support at the periphery while the wafer center remains unsupported, allowing precise control of the grinding interface while accommodating wafer flexibility. This localized support strategy prevents both excessive warping and grinding imprecision.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces the overall thickness of semiconductor devices while maintaining strength, preventing damage such as cracking and breakage, and allows for stable grinding processes.

Implementation Method 1

a semiconductor chip grinding process for grinding rear surfaces of the other semiconductor chips by a grinding apparatus while the wafer having the other semiconductor chips bonded thereon is held such that the rear surface of the wafer faces a chuck table of the grinding apparatus

Methodology Applied
Scientific EffectGrinding: Abrasion

Data Source

PatentUS7648889B2Production method for device
Publication Date: 2010.01.19 DISCO CORP
  • US7648889B2 patent drawing
  • US7648889B2 patent drawing
  • US7648889B2 patent drawing

AI summary

A production method for devices includes: a bonding process for placing circuit surfaces of other divided plural semiconductor chips onto circuit surfaces of semiconductor chips of a wafer and bonding the other semiconductor chips to the semiconductor chips of the wafer; and a semiconductor chip grinding process for grinding rear surfaces of the other semiconductor chips by a grinding apparatus while the wafer is held such that the rear surface of the wafer faces a chuck table of the grinding apparatus. The production method further includes a resin filling process for filling a resin on the surface of the wafer so that a surface of the resin corresponds with the rear surfaces of the other semiconductor chips; and a wafer grinding process for grinding the rear surface of the wafer by a grinding apparatus while the wafer is held such that the surface of the wafer on which the resin is filled faces a chuck table of the grinding apparatus. The production method further includes a wafer supporting process for supporting one of the surface and the rear surface of the wafer by a supporting member; and a dividing process for dividing the wafer along predetermined division lines while the wafer is supported by the support member, thereby obtaining devices having the semiconductor chips and the other semiconductor chips bonded on the semiconductor chips.