Wafer-Level Thin-Film Inductor Packaging for Shorter IC Paths
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Solution Overview
Problem
Integrated circuits (ICs) coupled with inductors on a printed circuit board (PCB) occupy significant footprint, increasing costs and have significant electrical path lengths that adversely affect circuit performance.
Innovation Solution
The integration of thin-film inductors (TFIs) directly on the IC die, such as a power management IC (PMIC), reduces PCB footprint and shortens electrical paths by forming TFIs on the IC die, using magnetic and insulating layers with redistribution layers (RDLs) and solder bumps for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If inductors are mounted on a printed circuit board (PCB) separately from the IC, then the IC and inductors can be electrically coupled through metallization traces, but the PCB footprint occupied increases significantly and the electrical path length between IC and inductors increases
Solution Approach 1:
The patent merges the IC and inductor into a single integrated structure where the inductor is formed directly on the IC substrate. The inductor windings are created using metallization layers deposited and patterned on the same substrate as the IC, eliminating the need for separate inductor components and their associated PCB mounting space. This integration directly reduces the overall PCB footprint while maintaining electrical coupling.
Solution Approach 2:
The patent transitions from a planar PCB layout where ICs and inductors are separate components to a three-dimensional integrated structure. The inductor windings are formed in multiple metallization layers stacked vertically on the IC substrate, utilizing the vertical dimension to create compact inductor structures that occupy minimal PCB area while achieving the required inductance values.
2Ease of manufacture
If inductors are mounted on a printed circuit board (PCB) separately from the IC, then the IC and inductors can be electrically coupled through metallization traces, but the electrical path length between IC and inductors increases
Solution Approach 1:
By integrating the inductor directly on the IC substrate, the patent eliminates the long metallization traces required to connect separate IC and inductor components on a PCB. The inductor windings are formed in close proximity to the IC pads, reducing the electrical path length to minimal trace lengths within the same substrate, thereby improving signal integrity and reducing parasitic effects.
3Area of stationary object
If thin-film inductors are formed directly on the IC die, then PCB footprint is reduced and electrical path lengths are shortened, but additional fabrication processes including multiple layers and dummy carrier wafers are required
Solution Approach 1:
The patent employs dummy carrier wafers that are prepared in advance with bonding layers and insulating layers before the actual inductor formation. These preliminary structures are attached to the IC die, and the inductor metallization layers are deposited and patterned on top. This preliminary preparation simplifies the overall fabrication process by pre-organizing the complex multi-layer structure before final assembly, making the process more manageable despite its complexity.
Solution Approach 2:
The patent introduces dummy carrier wafers as intermediary structures that facilitate the formation of thin-film inductors on the IC die. These carrier wafers provide mechanical support and a platform for depositing and patterning the inductor metallization layers. After the inductor is formed, the dummy carrier wafer is removed, leaving the integrated inductor structure. This intermediary approach enables complex multi-layer inductor fabrication while maintaining process control.
Data Source
AI summary
An aspect relates to a method of forming an integrated circuit (IC) package, including: forming a thin-film inductor (TFI) over a first dummy carrier wafer; attaching an integrated circuit (IC) die to and over the TFI; attaching a second dummy carrier wafer to and over the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to and under the TFI; and removing the second dummy carrier wafer from the IC die. Another aspect relates to a method of forming an IC package, including forming a first redistribution layer (RDL) over a through-silicon via (TSV); forming a second RDL under the TSV; forming a thin-film inductor (TFI) over the first RDL; and attaching at least one integrated circuit (IC) die to the second RDL or the TFI.