Wafer Level Interconnect Structure Using Temporary Substrate
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in achieving wafer level package integration due to limitations in substrate materials with low glass transition temperatures and significant inter-wafer and intra-wafer registration variations, which hinder the formation of reliable and high-density interconnect structures.
Innovation Solution
A method involving the use of a temporary substrate for forming a wafer level interconnect structure, including a series of insulating and conductive layers, followed by mounting semiconductor dies and encapsulating them, allows for the formation of conductive bumps and under bump metallization, enabling efficient electrical connections and improved manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional substrate materials with low glass transition temperature are used, then ease of manufacture is improved, but manufacturing precision deteriorates due to significant inter-wafer and intra-wafer registration variations
Solution Approach 1:
The patent introduces a carrier substrate as an intermediary component between the semiconductor wafer and the final package. This carrier substrate has a high glass transition temperature (greater than 200°C) and serves as a stable platform that maintains registration accuracy during high-temperature processing. The carrier substrate acts as a mediator that allows the semiconductor die to be processed at elevated temperatures without suffering from the registration variations that plague traditional low-Tg substrates.
Solution Approach 2:
The patent changes the critical parameter of glass transition temperature from low (traditional substrates) to high (carrier substrate greater than 200°C). This parameter change enables the substrate to maintain dimensional stability and registration accuracy at high processing temperatures, while still allowing ease of manufacture through the carrier substrate approach. The high Tg parameter resolves the contradiction by providing thermal stability without compromising manufacturability.
2Reliability
If higher processing temperatures are used, then electrical connectivity is improved, but substrate material limitations are exceeded due to low glass transition temperature
Solution Approach 1:
The carrier substrate serves as a thermal intermediary that can withstand high processing temperatures (greater than 200°C) without degrading. This intermediary allows the semiconductor die to be processed at elevated temperatures for improved electrical connectivity and solder joint reliability, while the carrier substrate itself remains stable and does not suffer from the low-Tg limitations of traditional substrates.
Solution Approach 2:
The patent changes the glass transition temperature parameter of the substrate from low to high (greater than 200°C), enabling the system to operate at higher processing temperatures. This parameter change directly resolves the contradiction by allowing elevated temperature processing for improved electrical connectivity while avoiding the material degradation that would occur with traditional low-Tg substrates.
3Productivity
If wafer level processes are used, then productivity is improved, but device complexity increases due to multiple encapsulant deposition and curing steps
Solution Approach 1:
The patent merges multiple encapsulant deposition and curing steps into a single integrated process. Instead of depositing and curing each encapsulant layer separately, the method deposits multiple encapsulants in sequence and then cures them simultaneously in a single curing step. This merging of operations maintains the productivity benefits of wafer-level processing while reducing the overall process complexity and cycle time.
Solution Approach 2:
The patent performs preliminary deposition of multiple encapsulants before performing the curing action. By depositing all required encapsulant layers in advance and then curing them simultaneously, the process eliminates the need for intermediate curing steps between each encapsulant deposition. This preliminary action approach streamlines the process while maintaining wafer-level productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of wafer level chip scale packages with enhanced electrical connectivity, reduced signal propagation, and improved manufacturability by allowing higher processing temperatures and better registration accuracy, thus overcoming the limitations of traditional substrate materials.
Implementation Method 1
A first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously.
Data Source
AI summary
A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the temporary substrate using wafer level processes. The wafer level processes include forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer. A first semiconductor die is mounted over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer, and a first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously. The temporary substrate is removed to expose the first passivation layer.