Wafer-Level LED Structure Using Through-Vias for Compact Packaging
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Solution Overview
Problem
Conventional methods for manufacturing light-emitting diode (LED) devices, such as wire bonding and flip chip processes, are inefficient and costly due to space wastage and complexity, respectively.
Innovation Solution
A wafer-level process involving eutectic bonding and through-vias (TGVs/TSVs) to create conductive paths from the top to the bottom of the LED wafer, allowing for surface mounting without bond wires or complex flip chip structures, using a carrier wafer with alignment marks for precise alignment and electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect LED die to package substrate, then electrical connectivity is achieved, but space is wasted and light may escape from the sides
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical connections through through-wafer vias. Electrical connections are established by forming conductive paths through the entire wafer thickness, allowing top and bottom surfaces to be electrically connected without lateral wire bonds, thus eliminating space waste and light leakage issues.
Solution Approach 2:
The patent removes the bond wires from the system entirely by implementing direct through-wafer electrical connections. The wire bonding step is extracted and replaced with integrated conductive vias formed during wafer fabrication, eliminating the harmful factors associated with wire bonds while maintaining electrical connectivity.
2Area of stationary object
If flip chip process is used to connect LED die to package substrate, then space efficiency is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent performs electrical connection formation during the wafer fabrication stage before die separation. Through-wafer vias and conductive layers are created while the wafer is still intact, allowing subsequent die to be mounted in any orientation without requiring complex flip chip processes. This preliminary action simplifies manufacturing while achieving space efficiency.
Solution Approach 2:
The through-wafer via structure serves multiple functions: providing electrical connections, enabling thermal management, and allowing flexible mounting orientations. This universal approach replaces the need for orientation-specific flip chip processes, reducing manufacturing complexity while maintaining space efficiency.
3Reliability
If conventional LED manufacturing processes are used, then proven reliability is maintained, but manufacturing efficiency and cost-effectiveness are reduced
Solution Approach 1:
The patent merges multiple separate manufacturing steps into an integrated wafer-level process. Electrical connections, thermal management paths, and optical structures are formed simultaneously during wafer fabrication rather than as separate post-die operations. This consolidation maintains reliability through proven semiconductor processes while dramatically improving manufacturing efficiency.
Solution Approach 2:
The wafer-level structures are designed to provide their own electrical connections and thermal management capabilities without requiring external wire bonds or complex packaging. The through-wafer vias and integrated conductive layers make the LED structure self-sufficient, reducing manufacturing steps and improving productivity while maintaining device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces space usage and simplifies the manufacturing process, eliminating the need for bond wires and complex internal metal interconnects, thereby enhancing efficiency and reducing costs while maintaining effective electrical connectivity.
Implementation Method 1
The epi wafer is eutectic bonded to a carrier wafer
Data Source
AI summary
A light-emitting device includes a first epi-structure with a top surface and a bottom surface opposite to the top surface, a first metal element and a second metal element disposed on the bottom surface, a first through-via, a conductive element disposed on the top surface, and a phosphor layer disposed on the top surface and covering the conductive element. The first epi-structure includes a first doped semiconductor layer, a second doped semiconductor layer closer to the bottom surface than the first doped semiconductor layer, and a light-emitting layer disposed between the first and second doped semiconductor layers. The first through-via extends through the first doped semiconductor layer and the second doped semiconductor layer and is electrically connected to the first doped semiconductor layer and the second metal element. The conductive element is in a configuration to expose a portion of the top surface, and electrically connected to the first through-via.