Wafer-Level Lidded Chip Fabrication With Electrodeposited Dielectric Coating
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Solution Overview
Problem
Heretofore, wafer-level packaging processes have not been available for fabricating semiconductor chips with pin-grid array interfaces or compliant ball-grid array interfaces while maintaining low costs and incorporating controlled impedance transmission lines for high-speed performance.
Innovation Solution
A method of fabricating a semiconductor element with conductive and semiconductive materials exposed at both surfaces, where an insulative layer is electrodeposited to form conductive traces on both surfaces and edge traces connecting them, allowing for the formation of packaged chips with pin-grid or ball-grid interfaces and controlled impedance transmission lines during wafer-level processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level packaging processes are used to fabricate chips with pin-grid array interfaces or compliant ball-grid array interfaces, then manufacturing cost is reduced and productivity is improved, but the ability to incorporate controlled impedance transmission lines for high-speed performance was previously unavailable
Solution Approach 1:
The packaging process is segmented into distinct stages: wafer-level processing for mass production, followed by post-dicing assembly for final package completion. This allows wafer-level packaging to handle multiple chips simultaneously while controlled impedance features are added to individual chips after dicing, resolving the contradiction between high-volume manufacturing and high-speed signal integrity
Solution Approach 2:
Basic packaging structures are preliminarily formed at the wafer level including substrate attachment and initial protective coatings. The controlled impedance transmission lines and pin-grid array interfaces are then added as preliminary features before final packaging completion, enabling both cost-effective mass production and high-performance signal transmission
2Ease of manufacture
If chips are packaged at the wafer level while remaining attached together, then manufacturing cost is reduced and processing efficiency is improved, but device complexity increases due to the need for post-dicing assembly steps
Solution Approach 1:
The manufacturing process is divided into two segments: wafer-level processing that handles multiple chips simultaneously for cost efficiency, and post-dicing assembly that completes individual chip packaging. This segmentation allows each stage to be optimized independently, reducing overall manufacturing complexity despite the multi-stage nature of the process
Solution Approach 2:
The wafer-level processing equipment performs multiple functions: substrate attachment, protective coating application, and preliminary structuring for all chips simultaneously. This multi-functionality reduces the need for separate specialized equipment for each packaging step, thereby reducing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the simultaneous packaging of multiple chips with integrated pin-grid or ball-grid interfaces and controlled impedance transmission lines, reducing costs and enhancing high-speed performance by maintaining the compactness of chip dimensions and interconnections.
Implementation Method 1
An insulative layer is electrodeposited onto the at least one of exposed semiconductive material or conductive material, forming (i) a plurality of rear conductive traces overlying the rear surface, (ii) a plurality of front conductive traces overlying the front surface in conductive communication with the first conductive contacts and (iii) a plurality of edge conductive traces extending along edge surfaces between the front and the rear conductive traces.
Data Source
Figure 1
Figure 2~3
Figure 4A~4B
AI summary
A unit including a semiconductor element, e.g., a chip-scale package (350, 1350) or an optical sensor unit (10) is fabricated. A semiconductor element (300) has semiconductive or conductive material (316) exposed at at least one of the front (302) and rear surfaces (114) and conductive features (310) exposed thereat which are insulated from the semiconductive or conductive material. By electrodeposition, an insulative layer (304) is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts (308) and a plurality of conductive traces (306) are formed overlying the electrodeposited insulative layer (304) which connect the conductive features (310) to the conductive contacts (308). An optical sensor unit (10) can be incorporated in a camera module (1030) having an optical element (1058) in registration with an imaging area (1026) of the semiconductor element (1000).