Wafer-Level Semiconductor Packaging With Mask-Based Conductive Patterning
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Solution Overview
Problem
The existing semiconductor packaging processes, particularly in wafer level packaging, are time-consuming due to the complexity of photolithography processes involving photoresist application, exposing, developing, and etching, which hinder efficient formation of conductive patterns.
Innovation Solution
An apparatus comprising a loading unit, deposition unit, and unloading unit, utilizing mask members to form conductive pattern layers on wafers in a single process, minimizing the number of steps and improving productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used to form conductive pattern, then conductive pattern can be formed on wafer, but packaging time becomes very long due to multiple complicated steps
Solution Approach 1:
The patent extracts and removes the photoresist application, exposing, developing, and etching steps from the traditional photolithography process. Instead, it uses a simplified approach where a conductive paste is directly applied through a mask and cured, eliminating unnecessary intermediate steps while still achieving the desired conductive pattern formation.
Solution Approach 2:
The patent skips the traditional multi-step photolithography process (photoresist application, exposing, developing, etching, photoresist removal) and rushes through to the essential outcome by directly applying conductive paste through a mask and curing it, thereby significantly reducing packaging time while maintaining pattern formation capability.
2Productivity
If wafer level packaging is used to package multiple semiconductor elements, then packaging efficiency is improved, but conductive pattern formation becomes time-consuming due to photolithography complexity
Solution Approach 1:
The patent extracts the time-consuming photolithography steps (photoresist application, exposing, developing, etching) from the wafer level packaging process and replaces them with a simplified direct paste application method, maintaining productivity benefits while eliminating the time bottleneck in conductive pattern formation.
Solution Approach 2:
The patent skips the complicated photolithography sequence and rushes through to functional conductive pattern formation by directly applying and curing conductive paste, thereby preserving wafer level packaging efficiency while dramatically reducing the time required for conductive pattern formation.
3Manufacturing precision
If traditional photolithography process is used, then conductive pattern can be formed, but material costs increase due to multiple process steps
Solution Approach 1:
The patent extracts and eliminates the need for photoresist materials and associated chemicals required in traditional photolithography. By using direct paste application through a mask followed by curing, it reduces material consumption and costs while still achieving precise conductive pattern formation.
Solution Approach 2:
The patent skips the material-intensive photolithography process steps and rushes through to conductive pattern formation using minimal materials (conductive paste and mask), thereby reducing material costs while maintaining manufacturing precision for conductive pattern formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The apparatus reduces packaging time and material costs by forming conductive patterns efficiently on wafers with mask members, enhancing semiconductor chip production efficiency.
Implementation Method 1
a sputtering target part installed inside the deposition chamber to face the support part
Data Source
AI summary
Provided is an apparatus for packing a semiconductor, and more particularly, to an apparatus for packing a semiconductor, which packages a semiconductor element in a wafer level packaging manner. The apparatus for packaging the semiconductor includes a loading unit having a space in which a process of disposing a mask member on a wafer including a plurality of semiconductor elements is performed, a deposition unit having a space, in which a process of transferring the wafer and the mask member from the loading unit to form a conductive pattern layer on the wafer is performed, and connected to the loading unit, and an unloading unit having a space, in which a process of transferring the wafer and the mask member from the deposition unit to separate the mask member from the wafer is performed, and connected to the deposition unit.