Wafer Level Metallization Trench Isolation for Chip Scale Packages
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Solution Overview
Problem
Conventional wafer-level packaging methods are inadequate for forming chip scale packages, as they often result in shorting between contacts and the silicon bulk or adjacent contacts, and cannot efficiently reduce package size and fabrication costs for discrete semiconductor devices.
Innovation Solution
The method involves forming trenches in a semiconductor substrate with insulating and conductive layers, selectively depositing fill materials, and separating the substrate along these trenches to create solderable surfaces without shorting, allowing for the formation of chip scale packages with reduced size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer-level packaging methods are used, then manufacturing simplicity is maintained, but shorting occurs between contacts and silicon bulk or adjacent contacts
Solution Approach 1:
The packaging structure is segmented into distinct functional regions: trenches separate adjacent contacts, insulator layers line the trenches to provide electrical isolation, and fill materials occupy specific portions of the trenches. This segmentation prevents shorting between contacts and the silicon bulk while maintaining contact isolation reliability.
Solution Approach 2:
Different materials and structures are applied to different locations: conductive material is deposited only on exposed substrate surfaces where solderable contacts are needed, while insulator layers line the trench regions. This local differentiation ensures electrical isolation in trench areas while maintaining conductivity at contact points, resolving the shorting issue without excessive complexity.
2Volume of moving object
If discrete semiconductor devices are packaged using traditional methods, then device functionality is achieved, but package size is much larger than the actual chip
Solution Approach 1:
The packaging approach transitions from three-dimensional encapsulation with mold compound to a two-dimensional planar structure where contacts lie substantially in the plane of the chip surface. This dimensional change eliminates the need for deep encapsulation structures, significantly reducing package volume while maintaining electrical functionality and simplifying fabrication processes.
Solution Approach 2:
The traditional mold compound encapsulation is extracted and replaced with a planar contact structure. By removing the bulky encapsulation material and using direct metallization with trench isolation, the package size is reduced to chip scale while maintaining the necessary electrical isolation and connectivity functions.
3Ease of operation
If trenches are formed and filled with conductive material, then solderable surfaces are created, but risk of shorting between adjacent contacts increases
Solution Approach 1:
An insulator layer is introduced as an intermediary material that lines the trenches between adjacent contacts. This insulator acts as a mediator that physically separates and electrically isolates the conductive material in adjacent trenches, preventing shorting while allowing each contact to maintain its solderable surface. The insulator layer thus enables both solderability and isolation simultaneously.
Solution Approach 2:
The insulator layer is deposited on the trench sidewalls before filling with conductive material, creating a preliminary barrier that prevents the conductive material from bridging between adjacent contacts. This preliminary protective action ensures that even if the fill material extends toward adjacent trenches, the insulator layer maintains electrical isolation and prevents shorting.
Data Source
AI summary
In one embodiment, a method for forming the semiconductor device includes forming a first trench from a front side of a substrate. The substrate has a front side and an opposite back side, and the first trench having sidewalls and a bottom surface. A insulator layer is formed over the sidewalls and the bottom surface. A first conductive layer is formed over a top portion of the sidewalls of the first trench. The substrate is separated along the first trench.