Wafer-Level Microsystem Packaging with Embedded Interconnects
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Solution Overview
Problem
Conventional integrated circuit packaging techniques are limited in providing cost-effective solutions for various packaging applications, particularly in integrating multiple interconnect layers and components into a single package while ensuring efficient heat dissipation and sensor integration.
Innovation Solution
A wafer level method involving a substrate with metal vias and multiple layers of photo-imageable epoxy, where interconnect layers are embedded within the epoxy and electrically coupled with the substrate, allowing for the formation of microsystems that include integrated circuits, sensors, and heat sinks, which are then encapsulated and singulated to create individual packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple interconnect layers and components are integrated into a single package, then device functionality and performance are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The package is divided into modular components: a substrate providing mechanical support, multiple discrete interconnect layers (first, second, and third interconnect layers) that can be independently formed and positioned, and separate component locations. This segmentation allows each layer and component to be manufactured and tested independently before final assembly, reducing overall manufacturing complexity while maintaining high device functionality.
Solution Approach 2:
The patent utilizes three-dimensional stacking with interconnect layers positioned at different heights and depths within the package. The first interconnect layer is formed on the substrate, the second interconnect layer is positioned above the first, and the third interconnect layer extends between them. This vertical dimensionality allows multiple functions to be integrated in a compact space without proportionally increasing manufacturing complexity.
2Temperature
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but heat dissipation efficiency and sensor integration capability are insufficient
Solution Approach 1:
The patent introduces a dedicated heat sink component as an intermediary thermal management element. The heat sink is thermally coupled to the substrate and provides a specialized pathway for heat dissipation from the integrated components. This intermediary structure addresses thermal management requirements without fundamentally changing the conventional packaging manufacturing process, maintaining ease of manufacture while significantly improving heat dissipation efficiency.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support for the package, acts as a mounting platform for the first interconnect layer and components, provides electrical connections through metal vias, and serves as a thermal conduction path to the heat sink. This multi-functionality reduces the need for additional specialized components, maintaining manufacturing simplicity while achieving effective heat dissipation.
3Adaptability or versatility
If components are arranged in fixed positions, then manufacturing precision is easier to achieve, but flexibility in component arrangement and thermal management is reduced
Solution Approach 1:
The package structure is segmented into distinct layers and regions with standardized interfaces. Each interconnect layer and component location is defined by standard patterns and dimensions, allowing components to be positioned flexibly within their designated zones while maintaining precise electrical and thermal connections through the standardized layer interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of cost-effective, high-performance integrated circuit packages with efficient heat dissipation and sensor integration, addressing the limitations of existing packaging techniques by allowing for flexible component arrangement and improved thermal management.
Implementation Method 1
A substrate with vias can be formed by forming holes in a substrate and electroplating an electrically conductive material into the holes
Implementation Method 2
Molding material is applied over the top surface of the substrate and the microsystems to form a molded structure
Data Source
AI summary
Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias.