Wafer Level Semiconductor Module with Scribe Line Sealing

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Solution Overview

Problem

Conventional semiconductor module manufacturing processes are complex, time-consuming, and cost-ineffective, with limitations in reducing module size and accommodating multiple IC chips efficiently.

Innovation Solution

A wafer level semiconductor module with IC chips mounted on a module board, featuring sealing portions in scribe line areas to absorb thermal stresses and prevent electrical interference, using a polymer or elastomer composition for sealing, and external connection terminals for efficient chip integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional semiconductor package assembly processes are used, then each IC chip can be individually packaged and tested, but the manufacturing process becomes complicated, time-consuming, and cost-ineffective

Engineering Contradiction:

Improveindividual chip packaging and testingVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple individual chip packaging operations into a single wafer-level packaging process. Multiple IC chips are packaged together on the wafer substrate simultaneously, eliminating the need for separate packaging and testing of each chip. This combining of operations reduces manufacturing complexity while maintaining the reliability benefits of individual chip packaging through the unified wafer-level approach.

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If multiple IC chips are mounted on a module board using conventional methods, then functional integration is achieved, but the module size cannot be effectively reduced

Engineering Contradiction:

Improvemultiple IC chip integrationVSAvoidmodule size

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements a nested structure where multiple IC chips are integrated within a compact wafer-level package that is itself mounted on the module board. The chips are arranged in a space-efficient configuration on the wafer substrate, with sealing portions filling the inter-chip spaces. This nesting approach allows multiple chips to occupy minimal area while maintaining full functionality, thereby reducing the overall module size.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Ease of manufacture

If scribe line areas between adjacent IC chips are left empty, then chip separation is simplified, but thermal stresses cause warpage and electrical interference occurs

Engineering Contradiction:

Improvechip separationVSAvoidthermal stress, warpage, and electrical interference

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent introduces sealing portions as intermediary elements that fill the scribe line areas between adjacent IC chips. These sealing portions act as mediators that provide mechanical support to prevent warpage from thermal stresses, while simultaneously providing electrical isolation to prevent interference between adjacent chips. The sealing portions are applied in a controlled manner that maintains ease of manufacture while eliminating the harmful effects of empty scribe lines.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution simplifies the manufacturing process, reduces module size, increases chip density, and enhances thermal and electrical performance by absorbing mechanical and thermal stresses, while preventing warpage and electrical interference.

Implementation Method 1

sealing portions provided in scribe line areas to absorb thermal stresses and prevent electrical interference

Methodology Applied

Scientific EffectThermal stress absorption: Thermal Expansion

Implementation Method 2

sealing portions provided in scribe line areas to absorb thermal stresses and prevent electrical interference

Methodology Applied

Scientific EffectMechanical stress absorption: Elasticity

Implementation Method 3

sealing portions provided in scribe line areas to absorb thermal stresses and prevent electrical interference

Methodology Applied

Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS8110922B2Wafer level semiconductor module and method for manufacturing the same

Publication Date: 2012.02.07 SAMSUNG ELECTRONICS CO LTD

AI summary

A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.