Wafer Level Molding Structure Using Anisotropic Conductive Adhesive
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Solution Overview
Problem
The existing chip-to-wafer (COW) bonding technique faces challenges with insufficient known-good dies (KGD), high manufacturing costs, and reduced production yield due to thermal expansion mismatch and the complexity of underfilling and molding processes, especially at fine pitches and thin chip thicknesses.
Innovation Solution
A wafer level molding structure and manufacturing method that uses a combination of through electrodes and an adhesive material, such as anisotropic conductive adhesive (ACA), to electrically connect chips and cover lateral sides, reducing the number of manufacturing steps and materials used, thereby minimizing thermal expansion issues and fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional COW packaging technique with underfilling process is used, then chips can be electrically connected and protected, but manufacturing cost increases and production yield decreases due to multiple steps and thermal expansion mismatch
Solution Approach 1:
The patent combines the underfilling process and molding process into a single integrated wafer-level molding process. The adhesive material serves dual functions: it acts as both the underfill that flows into gaps between chips for electrical connection and protection, and as the molding material that encapsulates the entire chip stack. This merging eliminates the need for separate underfill dispensing and molding steps, reducing manufacturing complexity and improving production yield by minimizing process variations and thermal expansion mismatch between different materials.
Solution Approach 2:
The adhesive material performs multiple functions simultaneously: it provides electrical connection through conductive particles, offers mechanical bonding between chips, serves as underfill to protect electrical connections, and acts as molding material for encapsulation. This multi-functionality reduces the number of different materials needed in the manufacturing process, simplifying the overall process and reducing thermal expansion mismatch issues that arise from using multiple different materials.
2Reliability
If three steps of stacking, underfilling and molding are performed, then chips can be assembled and protected, but manufacturing time increases and cost increases
Solution Approach 1:
The patent merges three separate manufacturing steps (stacking, underfilling, and molding) into a single wafer-level stacking and molding process. Chips are stacked on the wafer and the adhesive material is applied once to simultaneously achieve underfilling and molding functions. This integration reduces manufacturing time by eliminating two process steps while maintaining assembly quality through the dual-function adhesive material that ensures proper electrical connections and structural protection.
3Reliability
If different materials are used in underfilling process and molding process, then specific functions can be optimized, but fabrication cost increases
Solution Approach 1:
The adhesive material is designed to perform multiple functions that were previously required from different materials: it provides the flow and adhesion properties of underfill material and the encapsulation properties of molding material. This universality reduces fabrication cost by eliminating the need to source, store, and process multiple different materials, while still achieving the functional performance of electrical connection protection and mechanical support through the conductive particles and adhesive properties of the single adhesive material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces manufacturing costs and maintains production yield by simplifying the underfilling and molding processes, ensuring reliable electrical connections and minimizing thermal expansion mismatch, while allowing for finer pitch and thinner chip integration.
Implementation Method 1
an adhesive material is disposed between the first chip and the second chip and is covering the first lateral sides of the first chip
Implementation Method 2
The plurality of second through electrodes are disposed in the second chip and are used to electrically connect the second back side bumps and the second front side bumps of the second chip
Implementation Method 3
The first front side bumps of the first chip are electrically connected to the second back side bumps of the second chip
Data Source
AI summary
A wafer level molding structure including a first chip, a second chip and an adhesive layer therebetween is provided. The first chip includes a first back side, a first front side and a plurality of lateral sides, and a plurality of first front side bumps are disposed on the first front side. The second chip includes a second back side and a second front side, and a plurality of second back side bumps and second front side bumps are respectively disposed on the second back side and the second front side. A plurality of through electrodes are disposed in the second chip, and electrically connected the second back side bumps to the second front side bumps. Adhesive materials including a plurality of conductive particles cover the lateral sides, and electrically connect the second back side bumps with the first front side bumps.