Wafer-Level Multi-Die Packaging Without Wire Bonding
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Solution Overview
Problem
Current semiconductor device packaging technologies face challenges in integrating multiple chips efficiently, leading to increased package size, complexity, and reduced reliability due to the need for multiple substrates and wire bonding.
Innovation Solution
The method involves wafer-level processing techniques that eliminate one or more substrates and eliminate wire bonding, allowing for the direct electrical coupling of multiple semiconductor dice using a metal layer, which are then encapsulated in a molding compound to form a compact, reliable package assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple substrates and wire bonding are used to integrate multiple chips, then electrical connection between chips is achieved, but package size increases and device complexity increases
Solution Approach 1:
The patent merges multiple chip integration functions into a single substrate by directly mounting multiple semiconductor chips on one substrate and using conductive patterns formed on the substrate to establish electrical connections between chips, eliminating the need for separate substrates and wire bonding processes for each chip connection
Solution Approach 2:
The patent extracts and eliminates wire bonding from the packaging process by using conductive patterns formed directly on the substrate to create electrical connections between chips, thereby simplifying the package structure and reducing the number of components required
2Reliability
If multiple substrates are used to package multiple chips, then each chip can be properly supported, but the overall package size increases
Solution Approach 1:
The patent combines multiple chip mounting functions into a single substrate by providing a common substrate that supports multiple semiconductor chips, with conductive patterns formed on the substrate to establish electrical connections between the chips, thereby reducing the overall package area compared to using multiple separate substrates
3Reliability
If traditional packaging methods with multiple substrates are used, then proper electrical isolation is achieved, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent merges multiple packaging functions into a single integrated structure where one substrate supports multiple chips and provides both electrical connections and isolation through conductive patterns formed on the substrate, eliminating the need for multiple separate substrates and associated assembly steps, thereby improving manufacturing efficiency and productivity
Solution Approach 2:
The patent performs preliminary formation of conductive patterns on the substrate before mounting the semiconductor chips, allowing electrical connections to be pre-established on the substrate, which simplifies the subsequent chip mounting and wiring processes and improves overall manufacturing efficiency
Data Source
Figure 1~3
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Figure 4B
AI summary
In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.