Wafer-Level Optoelectronic Chip Testing With Parallel Optical Coupling

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Solution Overview

Problem

Existing wafer level test systems for photonic integrated circuits (PICs) are inefficient due to sequential and time-consuming optical coupling, lack of parallel contacting capabilities, and the need for costly and complex modifications to conventional wafer probers.

Innovation Solution

A method for testing optoelectronic chips on a wafer with electrical and optical interfaces, involving a positioning stage and a contacting module with adjustable electrical and optical interfaces, allowing for simultaneous alignment and coupling of optical signals with maximum efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If optical fiber-based systems with individual optical fibers are used for wafer level test, then optical coupling can be achieved, but the alignment procedure becomes time-consuming and sequential contacting is required

Engineering Contradiction:
Improveoptical coupling precisionVSAvoidthroughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The contacting module is divided into multiple independent contacting units, each capable of contacting and testing a specific chip or region. This segmentation allows parallel operation of multiple units simultaneously, increasing throughput while maintaining precise optical coupling capabilities in each unit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential one-dimensional contacting to parallel multi-dimensional contacting by arranging multiple contacting units in spatial arrays. This enables simultaneous contacting of multiple chips or multiple regions of a wafer, dramatically improving productivity while maintaining measurement precision through dedicated alignment mechanisms for each unit.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If conventional wafer probers are modified to support optical testing, then optical coupling capability is achieved, but the device complexity and modification cost increase

Engineering Contradiction:
Improveoptical testing capabilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The contacting module is designed with multi-functionality, integrating both electrical contacting capabilities (through needle contacts) and optical coupling capabilities (through optical fibers or waveguides) within a single unified structure. This allows the same module to perform both electrical and optical testing functions, reducing the need for separate dedicated optical testing equipment and simplifying the overall system architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges electrical contacting elements and optical coupling elements into a single integrated contacting module. The electrical needles and optical fibers are positioned in fixed spatial relationships within the same module, allowing simultaneous electrical and optical contact during a single positioning operation, thereby reducing device complexity compared to separate electrical and optical testing systems.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If precise actuators with hexapods and piezo elements are used for optical fiber alignment, then sub-micrometer alignment accuracy is achieved, but the system cost and complexity increase

Engineering Contradiction:
Improvealignment accuracyVSAvoidactuator complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The contacting module is pre-aligned and pre-positioned during manufacturing with the optical fibers and electrical needles in their correct spatial relationships. This preliminary action eliminates the need for complex real-time alignment actuators during operation, as the alignment is established once during module fabrication and maintained through precise mechanical positioning of the entire module relative to the wafer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses the known geometric relationships and pitch dimensions of the wafer grid to calculate and position the contacting module without requiring complex active alignment. The regular periodic structure of the wafer serves as a template, allowing the use of simpler positioning mechanisms that rely on precise reproduction of the wafer's geometric pattern rather than complex active feedback alignment systems.

Inventive Principle:
Principle #26Copying

4Reliability

If separate electrical and optical contacting modules are used, then functional characterization is possible, but the testing process is not optimized for throughput

Engineering Contradiction:
Improvefunctional characterization accuracyVSAvoidtesting throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines electrical contacting needles and optical coupling fibers into a single integrated contacting module, allowing simultaneous electrical and optical contact during one positioning operation. This merging eliminates the need for separate sequential contacting operations, thereby optimizing throughput while maintaining the ability to perform comprehensive functional characterization through concurrent electrical and optical measurements.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12210057B2Wafer-level test method for optoelectronic chips
Publication Date: 2025.01.28 JENOPTIK OPTICAL SYSTEMS GMBH
  • US12210057B2 patent drawing
  • US12210057B2 patent drawing
  • US12210057B2 patent drawing

AI summary

A method for testing optoelectronic chips that are arranged on a wafer and comprise electric interfaces in the form of contact pads and optical interfaces, which are arranged in a fixed manner relative to the electric interfaces, in the form of optical deflecting elements, e.g. grating couplers, at a specified coupling angle. In the process, the wafer is adjusted in three adjustment steps in such a manner that one of the chips is positioned relative to a contacting module such that the electric interfaces of the chip and the contacting module are in contact with one another and the optical interfaces of the chip and the contacting module assume a maximum position of the optical coupling.