Wafer-Level Wiring Pattern Layout for Shock-Resistant Package Adhesion
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high reliability due to vulnerabilities in withstanding external shocks and ensuring strong adhesion between insulating layers and wiring patterns.
Innovation Solution
A semiconductor package design that includes a semiconductor chip with a chip pad, a first insulating layer with a first via hole, a first wiring pattern connected to the chip pad, a second insulating layer with a second via hole, and a second wiring pattern connected to the first wiring pattern. The first insulating layer has a thicker upper surface with greater surface roughness than its lower surface, enhancing adhesion and shock resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulating layers are made thicker to buffer external shocks, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by creating asymmetric surface roughness on the insulating layers - the upper surface has greater roughness than the lower surface. This localized differentiation allows the thicker insulating layers to provide shock buffering while the rough upper surface specifically enhances adhesion to wiring patterns, resolving the contradiction between reliability and manufacturing complexity
2Reliability
If surface roughness of insulating layers is increased to improve adhesion, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements local quality by differentiating surface roughness between the upper and lower surfaces of insulating layers. The upper surface is engineered with greater roughness to maximize adhesion to wiring patterns, while the lower surface maintains smoother characteristics. This localized approach improves adhesion strength without uniformly increasing manufacturing precision requirements across the entire structure
3Reliability
If asymmetric surface roughness is implemented on insulating layers, then adhesion improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by creating asymmetric surface roughness - the upper surface of each insulating layer has greater roughness than its lower surface. This localized structural differentiation specifically targets the interface between insulating layers and wiring patterns to enhance adhesion, while avoiding unnecessary complexity in other regions of the device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design enhances the reliability of semiconductor packages by providing a buffer against external shocks through thick insulating layers and improving adhesion between insulating layers and wiring patterns due to surface roughness, thereby reducing stress and ensuring better connectivity.
Implementation Method 1
as an upper surface of the first insulating layer and/or an upper surface of the second insulating layer have relatively large surface roughness, adhesion between the first insulating layer and a first wiring pattern and/or adhesion between the second insulating layer and a second wiring pattern may be enhanced
Data Source
AI summary
A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.