Wafer Level Package Antenna Shielding EMC
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Solution Overview
Problem
Current wafer level packaging technologies, such as eWLB and InFO, face limitations in design freedom and electromagnetic compatibility (EMC) due to the integration of antennas at the same level as chips, leading to unwanted interactions and radiation coupling issues.
Innovation Solution
A wafer level package design with a layered structure that includes a contacting layer, an antenna layer with integrated antennas, and a chip layer, where a shielding layer is placed between the antenna and chip layers, along with a rewiring layer, decoupling the chip and antenna levels and allowing for flexible design without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If antennas are integrated at the same level as chips in wafer level packaging, then device integration is improved, but electromagnetic compatibility deteriorates due to unwanted interactions and radiation coupling
Solution Approach 1:
The patent divides the package structure into distinct layers: a chip layer containing chips and a separate antenna layer containing antennas. This spatial segmentation prevents electromagnetic interference while maintaining integration benefits, as the antenna layer can be optimized independently without affecting chip performance.
Solution Approach 2:
The patent transitions from planar integration (antennas and chips at the same level) to vertical stacking (antennas in a separate layer above or below chips). This dimensional change allows full hemispherical radiation coverage without coupling issues, as the shielding layer blocks electromagnetic interactions between layers.
2Object-affected harmful factors
If shielding is added between antenna and chip layers, then electromagnetic compatibility is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the shielding layer: it provides electromagnetic shielding, serves as a reference plane for antenna radiation, and can be integrated with the rewiring layer. This merging approach adds minimal complexity while achieving multiple benefits simultaneously.
Solution Approach 2:
The shielding layer is designed to perform multiple functions: electromagnetic shielding, signal reference plane, and structural support. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
3Reliability
If antenna dimensions are adjusted to optimize radiation coverage, then antenna performance is improved, but design freedom is limited due to constraints on RDL and molding material dimensions
Solution Approach 1:
The patent separates antenna design from chip and package constraints by placing antennas in a dedicated layer. This allows independent optimization of antenna dimensions and geometry without being constrained by RDL or molding material dimensions, as the antenna layer can be designed separately and then integrated.
Solution Approach 2:
By moving antennas to a separate layer, the patent enables three-dimensional optimization of antenna configurations. Designers can adjust antenna dimensions, patterns, and orientations in the antenna layer without affecting the two-dimensional chip layout or package footprint, thereby restoring design freedom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides full shielding of antenna fields from chips and other components, preventing EMC issues and allowing antennas to radiate in the entire hemisphere without unwanted coupling, while enabling flexible design and optimization of antenna configurations.
Implementation Method 1
Between the antenna layer and the chip layer are means for shielding, such as. B. a screen plane or generally a screen is provided
Implementation Method 2
the radiation from an integrated antenna cannot cover the whole hemisphere (the entire horizontal and vertical plane) without causing unwanted coupling with other integrated components
Data Source
Figure 1
Figure 2a
Figure 2b
AI summary
A wafer-level package with an integrated antenna comprises a contact layer, an antenna layer with an integrated antenna, and a chip layer with at least one chip located between the contact layer and the antenna layer. Furthermore, shielding means are provided between the antenna layer and the chip layer.