Wafer-Level Semiconductor Package Carrier Removal
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Solution Overview
Problem
Conventional semiconductor packaging techniques require mounting semiconductor dice onto device carriers, limiting package size reduction and introducing mismatches in physical properties, leading to higher failure risks.
Innovation Solution
A method for manufacturing semiconductor packages by providing a semiconductor wafer with bond pads, covering it with a dielectric material, forming wells to expose the pads, depositing a conductive material, and singulating the wafer to create packages without the need for a device carrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor dice are mounted onto device carriers during packaging, then the packaging process can be completed, but the package size cannot be reduced further and the physical property mismatch increases failure risk
Solution Approach 1:
The invention extracts and eliminates the device carrier from the packaging process. By forming terminal contacts directly on the bond pads of the semiconductor die and singulating the wafer into individual packages, the carrier substrate is completely removed. This resolves the physical property mismatch between die and carrier that caused failure risks, while also enabling chip-scale package dimensions.
Solution Approach 2:
The invention merges the packaging process with the wafer fabrication process. Terminal contacts are formed on bond pads while the die are still mounted on the wafer, and the wafer is singulated into individual packages in the same processing sequence. This integration eliminates the need for separate die mounting steps, reducing process complexity and improving reliability.
2Reliability
If semiconductor dice are mounted onto device carriers, then electrical connections can be established, but inductance increases and electrical performance deteriorates
Solution Approach 1:
The invention removes the device carrier from the electrical connection path. By forming terminal contacts that extend through the dielectric layer to expose bond pads, and then singulating the wafer, the electrical connection is achieved directly between the bond pad and external terminals without the intermediate carrier substrate. This eliminates the inductance introduced by the carrier and improves electrical performance.
3Ease of manufacture
If conventional packaging techniques are used, then manufacturing experience is available, but package size is larger than necessary
Solution Approach 1:
The invention performs packaging operations while the semiconductor die are still in wafer form. Terminal contacts are formed on bond pads, dielectric layers are applied, and singulation is performed before the die are separated into individual packages. This preliminary packaging approach enables chip-scale dimensions while using standard wafer-level processing techniques that manufacturers already possess.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables smaller, low-inductance packages with improved electrical performance and reduced failure risks by directly forming terminal contacts on the dice, making the process cost-effective and minimizing electrical interference.
Implementation Method 1
covering the first side of the wafer with a dielectric material to form a dielectric layer over the bond pads
Implementation Method 2
depositing a conductive material into the wells to form a conductive layer between the bond pads and a top surface of the dielectric layer
Data Source
AI summary
During the manufacture of a semiconductor package, a semiconductor wafer including a plurality of bond pads on a surface of the wafer is provided and the surface of the wafer is covered with a dielectric material to form a dielectric layer over the bond pads. Portions of the dielectric layer corresponding to positions of the bond pads are removed to form a plurality of wells, wherein each well is configured to form a through-hole between top and bottom surfaces of the dielectric layer for exposing each bond pad. A conductive material is then deposited into the wells to form a conductive layer between the bond pads and a top surface of the dielectric layer. Thereafter, the semiconductor wafer is singulated to form a plurality of semiconductor packages.