Wafer Level Package Clearance Walls for Foreign Object Contamination

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Solution Overview

Problem

Wafer-level packaging methods often result in defective products due to foreign objects damaging circuit elements during processes like via hole formation and wiring deposition, as there are no obstacles to prevent foreign objects from entering internal wafer portions.

Innovation Solution

Incorporating clearance wall members on the external surfaces of element wall members to create clearance sections between circuit element sections, which act as obstacles to prevent foreign objects from contaminating other regions of the wafer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wafer-level packaging is performed without internal partitions, then manufacturing simplicity is maintained, but foreign objects can freely move and contaminate multiple element sections, reducing product reliability

Engineering Contradiction:

Improveproduct reliabilityVSAvoidpackage structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The package structure is segmented into element sections and clearance sections by clearance wall members. These partitions divide the internal space of the wafer member, creating isolated element sections that prevent foreign objects from moving between sections, while clearance sections provide controlled spaces for foreign object containment.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Clearance wall members act as intermediary structures between element sections. These walls serve as physical barriers that mediate the interaction between foreign objects and circuit elements, preventing direct contact and contamination while maintaining the overall package integrity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If clearance wall members are added to divide internal space, then foreign object contamination is prevented, but manufacturing complexity and process difficulty increase

Engineering Contradiction:

Improvecircuit element protectionVSAvoidmanufacturing process ease

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The clearance wall members are integrated with the wafer member structure, forming a unified component. This merging approach allows the partitions to be manufactured as part of the wafer member itself, reducing the number of separate assembly steps and simplifying the overall manufacturing process despite the increased structural complexity.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If traditional chip separation and packaging methods are used, then individual chip assembly is achieved, but manufacturing costs increase due to multiple materials and processes

Engineering Contradiction:

Improvemanufacturing cost reductionVSAvoidassembly process reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The wafer member serves multiple functions: it acts as the substrate for circuit elements, provides the package structure, and incorporates clearance wall members for foreign object protection. This multi-functionality eliminates the need for separate packaging materials and assembly steps, reducing manufacturing costs while maintaining reliability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10329142B2Wafer level package and method of manufacturing the same

Publication Date: 2019.06.25 SAMSUNG ELECTRO MECHANICS CO LTD

AI summary

A wafer level package includes a wafer member having inner cavities in which circuit elements are disposed, element wall members disposed on an internal surface of the wafer member and enclosing element sections in which the circuit elements are disposed, and clearance wall members disposed on external surfaces of the element wall members and dividing a space between the element sections into clearance sections.