Wafer-Level Microelectronic Package With Compliant Layer
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Solution Overview
Problem
Current wafer-scale microelectronic packaging methods face challenges with thermal expansion mismatch between semiconductor wafers and substrates, leading to reliability issues and increased costs due to the need for precise matching of coefficients of thermal expansion, and existing methods involve numerous processing steps that risk wafer loss during packaging.
Innovation Solution
A method involving a plate with aligned openings and a compliant layer, where electrically conductive features are attached to the plate, aligned with the wafer contacts, and wire bonds are formed to connect the conductive features to the wafer contacts, followed by encapsulation, minimizing processing steps and reducing thermal expansion mismatch by using a plate with a coefficient of thermal expansion matching the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-scale packaging is used to improve productivity, then manufacturing efficiency increases, but thermal expansion mismatch problems are exacerbated due to the larger size of the wafer-scale structure
Solution Approach 1:
The patent introduces a substrate as an intermediary component between the semiconductor wafer and the external environment. This substrate acts as a buffer that decouples the thermal expansion characteristics of the wafer from the packaging structure, allowing wafer-scale packaging to proceed without being constrained by CTE matching requirements. The substrate absorbs the thermal expansion differential, enabling high-productivity wafer-scale manufacturing while maintaining reliability.
2Reliability
If numerous processing steps are used to achieve precise CTE matching, then thermal expansion compatibility improves, but the risk of wafer loss and manufacturing complexity increase
Solution Approach 1:
The patent extracts the CTE matching requirement from the packaging process by introducing a substrate that assumes this function. Instead of performing multiple processing steps to match CTE between wafer and package, the substrate is designed with appropriate CTE characteristics from the outset, eliminating the need for complex matching procedures and reducing manufacturing complexity while ensuring thermal expansion compatibility.
3Reliability
If numerous processing steps are performed during packaging, then electrical interconnections can be established, but the risk of wafer loss increases
Solution Approach 1:
The patent performs preliminary actions by pre-attaching the substrate to the wafer before subsequent packaging steps. This early bonding establishes a stable foundation that protects the wafer during later processing operations. The substrate serves as a protective layer and handling interface, reducing the risk of wafer loss while enabling necessary electrical interconnections to be established in a controlled manner.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and cost-effectiveness of wafer-scale packaging by reducing processing steps, minimizing thermal expansion mismatch, and preventing wafer loss during packaging, while maintaining efficient electrical interconnections.
Implementation Method 1
a compliant layer, where electrically conductive features are attached to the plate, aligned with the wafer contacts
Implementation Method 2
wire bonds are formed to connect the conductive features to the wafer contacts
Implementation Method 3
followed by encapsulation, minimizing processing steps
Data Source
AI summary
A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer. After making the subassembly, the bottom surface of the plate is attached with the top surface of a semiconductor wafer so that the openings extending through the plate are aligned with contacts on the wafer. At least some of the electrically conductive features on the compliant layer are electrically interconnected with the contacts on the semiconductor wafer.