Wafer Level Package Panel Processing for Productivity

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Solution Overview

Problem

There is a need to improve the productivity and reduce the cost of the semiconductor package process using wafer level package technology, as existing methods do not efficiently address the challenges of cost reduction and productivity enhancement.

Innovation Solution

A method involving arranging multiple wafers on a tray, forming an interconnect structure with insulating layers and metal layers, and separating the wafers to create compact semiconductor packages with enhanced heat dissipation efficiency, allowing for simultaneous processing of multiple wafers in a panel level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wafer level package technology is used to reduce production cost, then manufacturing cost decreases, but productivity improvement is insufficient

Engineering Contradiction:
Improveproduction costVSAvoidproductivity
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

Multiple wafers are arranged and processed simultaneously on a single tray in a panel level configuration, merging multiple individual wafer processing operations into one unified processing step. This allows simultaneous formation of interconnect structures on multiple wafers, thereby improving productivity while maintaining the cost benefits of wafer level packaging

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The processing approach transitions from individual wafer processing to panel level processing by arranging multiple wafers in a two-dimensional array on a tray. This dimensional change enables parallel processing of multiple wafers simultaneously, achieving productivity improvement without compromising the cost effectiveness of wafer level package technology

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of stationary object

If wafer level package technology is used to reduce total thickness, then package thickness decreases and heat dissipation improves, but productivity remains limited

Engineering Contradiction:
Improvepackage thicknessVSAvoidproductivity
Core Design Contradiction:
Length of stationary objectVSProductivity

Solution Approach 1:

Multiple wafers are processed simultaneously on a single tray, merging multiple individual packaging operations into one unified process. This panel level processing maintains the thin profile benefits of wafer level packages while achieving significant productivity improvement through parallel processing of multiple wafers

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If traditional semiconductor package process is used, then manufacturing flexibility is maintained, but productivity is low and cost is high

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidproductivity
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The invention merges multiple individual wafer processing steps into a single panel level processing operation. Multiple wafers arranged on a tray are processed simultaneously for interconnect structure formation, achieving high productivity while maintaining manufacturing flexibility through the modular tray design and standardized processing steps

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10804146B2Method for producing semiconductor package
Publication Date: 2020.10.13 NEPES CO LTD
  • US10804146B2 patent drawing
  • US10804146B2 patent drawing
  • US10804146B2 patent drawing

AI summary

A technical concept of the present disclosure provides a method of producing a semiconductor package, the method including operations of: arranging a plurality of wafers on a tray, forming an interconnect structure on the tray and the plurality of wafers, and separating the plurality of wafers from the tray.