Wafer Level Semiconductor Package Using Pre-Formed Dielectric Layers
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Solution Overview
Problem
Conventional wafer level packaging processes are time-consuming, expensive, and environmentally harmful due to the use of chemical reagents and limitations in achieving uniform surface passivation layers greater than 5-10 microns, requiring multiple chemical processing steps and lithographic masking.
Innovation Solution
The method involves using pre-formed dielectric layers affixed through lamination and direct laser ablation to form redistribution layers and openings, reducing processing time and chemical reagent use, enabling uniform thicknesses greater than conventional spin coating, and allowing for faster production of wafer level semiconductor packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If spin coating process is used to apply surface passivation layers, then the layers can be formed on processed wafers, but the process is time consuming and expensive with multiple chemical processing steps
Solution Approach 1:
The patent applies preliminary action by pre-forming the passivation layer on the wafer before the packaging process. The passivation layer is formed as part of the wafer fabrication process, eliminating the need for separate spin coating and chemical processing steps during packaging. This advance preparation reduces both time and cost while maintaining manufacturing ease.
2Ease of manufacture
If lithographic masks are used to pattern passivation layers, then redistribution layers and under-bump metallization can be formed, but the process requires multiple chemical processing steps with environmentally harmful reagents
Solution Approach 1:
The patent extracts and eliminates the harmful chemical processing steps from the manufacturing process. Instead of using lithographic masks and chemical etchants to pattern the passivation layer, the invention uses mechanical or laser-based ablation methods that do not require environmentally harmful reagents, thereby removing the source of environmental harm while maintaining the ability to form redistribution layers and under-bump metallization.
Solution Approach 2:
The patent replaces the chemical-based lithographic masking system with a mechanical or laser-based ablation system. This substitution eliminates the need for chemical reagents and masks, reducing environmental harm while achieving the same patterning function for forming redistribution layers and under-bump metallization.
3Manufacturing precision
If conventional spin coating is used for passivation layers, then layers can be applied, but uniform thickness greater than 5-10 microns cannot be achieved
Solution Approach 1:
The patent applies parameter changes by modifying the deposition process parameters to achieve uniform thick layers. Instead of relying on spin coating which has inherent thickness limitations, the invention uses alternative deposition methods with adjusted parameters (such as CVD or PVD conditions) that enable uniform passivation layers exceeding 10 microns in thickness, thereby overcoming the thickness constraint while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces production time, eliminates costly chemical processing, and allows for thicker, more uniform dielectric layers, resulting in a faster, less costly, and environmentally cleaner wafer level semiconductor packaging solution.
Implementation Method 1
direct laser ablation to form redistribution layers and openings
Implementation Method 2
affixed using a lamination process
Data Source
AI summary
There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.