Wafer-Level Package Resin Coating and Grinding for Cost Reduction
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Solution Overview
Problem
Conventional wafer-level packaging methods for small-sized ICs, such as RFID and LED ICs, face low production efficiency and high equipment costs, leading to high product unit prices and inefficiencies in manufacturing thin small products.
Innovation Solution
A wafer-level package method involving forming metal bumps, applying a high polymer resin coating, grinding and cutting the wafer, and bonding the chips to an antenna or substrate using surface mounting technology, which includes printing techniques for endpoint formation and lamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single chip packaging methods are used, then each chip can be individually packaged, but production capability is low and equipment cost is very high
Solution Approach 1:
The patent merges multiple individual chip packaging operations into a single wafer-level packaging process. Multiple chips on a wafer are packaged simultaneously using one set of equipment, eliminating the need for separate packaging equipment for each chip and dramatically improving production capability while reducing equipment investment cost.
Solution Approach 2:
The wafer-level packaging equipment is designed to handle multiple chips simultaneously, making it a multi-functional system that can package many chips in one operation. This universal equipment replaces the need for multiple single-chip packaging machines, reducing overall equipment cost while increasing productivity.
2Productivity
If wafer-level package uses semiconductor manufacturing equipment, then production efficiency is high, but manufacturing cost is very high due to expensive equipment investment
Solution Approach 1:
The patent employs a simpler, less expensive packaging equipment design compared to full semiconductor manufacturing equipment. The equipment is optimized specifically for the packaging step rather than requiring complete semiconductor fabrication capabilities, reducing equipment investment cost while maintaining high wafer-level packaging efficiency.
3Length of stationary object
If conventional chip scale package is used, then chips can be packaged, but the package is too thick to make very thin small products
Solution Approach 1:
The patent changes the packaging approach from individual chip packaging to wafer-level packaging, which enables thinner package profiles. The wafer-level process allows for more efficient use of space and materials, reducing the overall package thickness to enable very thin small products while maintaining high production efficiency.
4Ease of manufacture
If sequential processes are used for single chip packaging, then chips can be packaged and assembled, but production capability is low and product unit price is very high
Solution Approach 1:
The patent combines multiple sequential packaging and assembly operations into an integrated wafer-level process. By performing packaging, grinding, and cutting operations on the entire wafer simultaneously rather than processing individual chips sequentially, the method dramatically improves production capability while keeping the manufacturing process manageable and cost-effective.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the cost-effective manufacturing of high-quality SMD products with mass production capabilities, reducing production costs and maintaining product quality.
Implementation Method 1
forming a metal bump on a wafer
Implementation Method 2
applying a high polymer resin coating
Implementation Method 3
grinding a surface of the resin; grinding and cutting
Implementation Method 4
grinding and cutting
Implementation Method 5
bonding the chips to an antenna or a substrate with SMT (surface mounting technology)
Data Source
AI summary
A wafer-level package and an IC module assembly method for a wafer-level package are provided in the present invention. The method comprises forming a metal bump on a wafer, applying a high polymer resin coating to the wafer, grinding a surface of the resin coating, printing an endpoint on the wafer, a grinding and cutting step and bonding the chips to an antenna or substrate with SMT. The present invention can be used to manufacture high quality chips of low cost with mass production to significantly reduce cost and maintain high quality of the products.