Wafer-Level Package Stacked Chips Heat Dissipation
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high integration density and low height to accommodate the increasing demand for multifunctional electronic products with high data processing capabilities, necessitating improved operation speed and integration density.
Innovation Solution
A wafer-level package is designed with a first semiconductor chip, a redistribution layer, a second semiconductor chip bonded using flip-chip bonding, copper posts, solder balls, and heat sinks to enhance integration density and operation speed, featuring a molding member that exposes the solder balls and allows for efficient heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor package structures are used, then manufacturing is simpler, but integration density and operation speed are insufficient
Solution Approach 1:
The patent implements a stacked package structure where a first semiconductor chip and a second semiconductor chip are vertically arranged with the second chip mounted on the first chip. This nested configuration increases integration density by utilizing the vertical dimension, allowing multiple functional components to be integrated within a compact footprint while maintaining manufacturability through established flip-chip bonding processes.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By arranging semiconductor chips in the vertical direction rather than only in the horizontal plane, the package achieves higher integration density without proportionally increasing the package footprint, thus resolving the contradiction between density and complexity.
2Length of stationary object
If package height is reduced for downscaled electronic products, then form factor is improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent introduces a molding compound as an intermediary material that fills the space between the stacked semiconductor chips and the package substrate. This molding compound serves dual functions: it mechanically supports the compact stacked structure to achieve low package height, and simultaneously provides thermal pathways through its thermally conductive properties to facilitate heat dissipation from the chips, thus resolving the contradiction between reduced height and heat management.
3Adaptability or versatility
If signal paths are lengthened for complex multifunctional packages, then functionality is improved, but operation speed decreases
Solution Approach 1:
The patent utilizes vertical stacking to achieve multifunctionality within a compact space. By arranging different functional chips (e.g., logic chip, memory chip, RF chip) in the vertical dimension rather than spreading them horizontally, the design enables complex multifunctional integration while keeping signal paths short. The vertical interconnections through the stack minimize signal transmission distance compared to horizontal routing, thus maintaining high operation speed despite enhanced functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reduced package height, simplified fabrication, and improved signal transmission speed by shortening signal paths and effectively managing heat generated by the semiconductor chips, thereby enhancing the performance and integration density of semiconductor packages.
Implementation Method 1
a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique
Implementation Method 2
a first heat sink disposed on a top surface of the first semiconductor chip... a second heat sink disposed on a bottom surface of the second semiconductor chip
Data Source
AI summary
A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.