Wafer Level Package for 3D IC Using Step Recess Underfill
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher integration density, smaller form factors, cost-effectiveness, increased performance, and reduced power consumption, particularly in packaging techniques for semiconductor dies, where traditional methods fail to efficiently reduce parasitic losses and achieve miniaturization.
Innovation Solution
The implementation of a wafer level package technology for three-dimensional integrated circuits (3D ICs) involves stacking semiconductor dies with interconnection bumps and through vias, using a two-step dicing process to create step recesses, and employing underfill and molding compound layers to reduce mechanical and thermal stresses, and facilitate efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional packaging techniques are used, then fabrication costs are reduced, but parasitic losses increase and integration density decreases
Solution Approach 1:
The patent transitions from traditional planar (2D) packaging to three-dimensional (3D) stacking architecture, where multiple semiconductor dies are vertically stacked and interconnected through bumps and through vias. This dimensional change shortens signal paths and reduces parasitic losses by eliminating long lateral interconnections, while maintaining cost-effectiveness through wafer-level processing techniques.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate semiconductor dies that are stacked vertically, with each die containing specific functional blocks. These segmented dies are interconnected through bumps and through vias, allowing independent optimization of each die while reducing overall parasitic losses compared to a single large die.
2Quantity of substance
If semiconductor process node is shrunk, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
Instead of shrinking a single large die to achieve higher integration density, the patent segments the circuit into multiple smaller dies stacked vertically. Each die can be manufactured using standard process nodes, avoiding the complexities of sub-20nm fabrication while achieving higher overall density through the 3D stacking architecture.
3Volume of moving object
If multi-chip wafer level package is employed, then form factor is reduced, but signal path length increases
Solution Approach 1:
The patent vertically stacks multiple semiconductor dies and connects them through bumps and through vias, transforming lateral signal paths into vertical interconnections. This 3D architecture dramatically shortens signal path lengths compared to planar arrangements, as signals travel directly upward through the stack rather than laterally across large distances.
4Loss of energy
If traditional wire bonding is used, then ease of manufacture is maintained, but parasitic losses and power consumption increase
Solution Approach 1:
The patent replaces traditional wire bonding (mechanical filament-based interconnection) with a semiconductor-based interconnection system using bumps and through vias. This substitution eliminates the high parasitic inductance and resistance associated with wire bonds, reducing energy losses and power consumption while maintaining manufacturability through standard semiconductor fabrication processes.
Data Source
AI summary
A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.