Wafer-Level Package With Thinned Die and Mold Compound Thermal Management
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Solution Overview
Problem
Conventional silicon substrates used in RF device fabrication suffer from harmonic distortion and low resistivity, which impede high-level linearity and quality factor performance, especially at high frequencies, and generate excessive heat due to high transistor density and speed, necessitating improved thermal and electrical packaging solutions.
Innovation Solution
A wafer-level package design incorporating a thinned die with a multilayer redistribution structure and mold compounds, featuring solder-free connections and high thermal conductivity materials, such as mold compounds with thermal conductivity greater than 2 W/m·K, to enhance heat dissipation and electrical performance without increasing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional silicon substrates are used for RF device fabrication, then manufacturing cost is reduced and production capacity is increased, but harmonic distortion increases and resistivity decreases
Solution Approach 1:
The patent extracts the silicon substrate from the RF device structure by using through-silicon vias (TSVs) that penetrate through the substrate, allowing the substrate to be removed or thinned. This extraction eliminates the harmful electrical properties of the silicon substrate (harmonic distortion and low resistivity) while maintaining the benefits of silicon-based manufacturing. The RF devices are then mounted on a different substrate or supported structure that does not exhibit these harmful electrical characteristics.
2Ease of manufacture
If conventional silicon substrates are used for RF device fabrication, then manufacturing cost is reduced and production capacity is increased, but quality factor at high frequencies decreases
Solution Approach 1:
The silicon substrate is extracted or removed from the high-frequency signal path by using TSVs that allow the substrate to be thinned or eliminated. This removes the source of quality factor degradation at high frequencies while preserving the manufacturing advantages of silicon-based production processes.
3Productivity
If high transistor density is integrated in RF devices, then device performance is improved, but heat generation increases
Solution Approach 1:
The patent introduces thermal management structures as intermediaries between the high-density transistor integration and the external environment. These structures include thermal vias, heat sinks, and thermally conductive materials that mediate the heat transfer from the dense transistor array, enabling high productivity while controlling temperature rise.
4Area of stationary object
If wafer-level packaging is used to increase I/O density, then package size is reduced, but thermal management becomes more challenging
Solution Approach 1:
The patent moves thermal management from a two-dimensional surface level to a three-dimensional vertical structure by implementing through-silicon vias and multi-layer thermal pathways. This dimensional transition allows heat to be conducted vertically through the wafer-level package structure, enabling effective thermal management in a compact footprint without increasing package area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces harmonic distortion, improves quality factors at high frequencies, and enhances thermal management, thereby addressing the limitations of conventional silicon substrates in RF device packaging.
Implementation Method 1
mold compounds with thermal conductivity greater than 2 W/m·K, to enhance heat dissipation
Data Source
AI summary
The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.