Wafer Level Package With Die Receiving Through-Hole
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Solution Overview
Problem
Conventional wafer level packaging techniques face issues with CTE mismatch between substrate materials and motherboards, leading to mechanical instability and increased manufacturing costs, and struggle to reduce chip size due to thickness and complexity in the packaging process.
Innovation Solution
A fan-out wafer level packaging structure with a substrate having die receiving through-holes, filled with elastic core paste and a redistribution layer, utilizing materials with CTE matching the motherboards to absorb thermal mechanical stress and reduce package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional WLP uses silicon die encapsulated by molding compound, then the die is protected and interconnected, but CTE mismatching causes chip location shift and mechanical instability
Solution Approach 1:
The patent changes the substrate material from conventional molding compound (CTE 40-80) to glass ceramic material (CTE 6-10), fundamentally altering the thermal expansion parameter to match silicon die. This parameter change eliminates CTE mismatching stress and prevents chip location shift during temperature cycling, directly resolving the mechanical instability issue.
Solution Approach 2:
The patent employs a composite structure consisting of glass ceramic substrate combined with dielectric layers and conductive patterns. This composite material system provides both mechanical support and electrical interconnection while maintaining CTE compatibility with the silicon die, thereby improving reliability without sacrificing functionality.
2Device complexity
If die are directly formed on the upper surface of the substrate, then the packaging process is simplified, but the build up layer increases package thickness
Solution Approach 1:
The patent transitions from planar die placement on the substrate surface to three-dimensional integration within through-holes. By utilizing the vertical dimension (depth of through-holes) rather than only horizontal surface area, the design accommodates die and interconnection structures without increasing overall package thickness, effectively resolving the contradiction between simplified packaging and thickness reduction.
Solution Approach 2:
The patent implements nesting by placing die inside through-holes of the glass ceramic substrate, and embedding conductive patterns and dielectric layers within and around the die structures. This nested arrangement maximizes space utilization and eliminates the need for additional build-up layers, maintaining compact package thickness while achieving complete packaging functionality.
3Manufacturing precision
If conventional package techniques are used to divide and package each die separately, then individual die can be optimized, but manufacturing time increases significantly
Solution Approach 1:
The patent merges multiple packaging operations into a single integrated process. Multiple die are simultaneously packaged within the same glass ceramic substrate using through-holes, combining what would traditionally be separate packaging operations. This merging approach maintains individual die optimization while dramatically improving manufacturing throughput by processing multiple units in parallel.
Solution Approach 2:
The glass ceramic substrate serves multiple functions simultaneously: providing mechanical support, enabling thermal management through CTE matching, facilitating electrical interconnection through embedded conductive patterns, and accommodating multiple die through through-hole structures. This multi-functionality eliminates the need for separate packaging components and processes for each die, improving productivity while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved reliability and reduced device size with excellent CTE performance, simplifying the manufacturing process and reducing costs by eliminating the need for complex mold tools and CMP processes, while ensuring stability during temperature cycling.
Implementation Method 1
filled with elastic core paste and a redistribution layer, utilizing materials with CTE matching the motherboards to absorb thermal mechanical stress
Data Source
AI summary
The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die disposed within the die receiving through hole; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.